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How Assertions Can Be Used for DesignPublication: eeDesign (EE Times EDA News) May 22, 2006 -- There has been a lot of talk in the industry about the usefulness of assertions as part of a complete verification methodology. But there is something bigger going on here that many vendors are missing - the value that properties can contribute to fundamental aspects of the design flow. By combining synthesis with data logging techniques, properties can be turned into full on-chip diagnostics, error logging or usage monitoring systems. Property languages are a perfect starting point for defining these capabilities. This paper will explore the expanded role for properties in both the verification and design domains. It will show examples from a tool called DiaLite from Temento Systems1. By Brian Bailey. (Bailey is the chief technologist at Poseidon Design Systems, Inc.) | |
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