Analog and Mixed-Signal Connectivity IP at 65nm and Below
Publication: EE Times EDA Designline
May 7, 2007 -- The demand for connectivity intellectual property (IP) for high-speed serial buses such as USB 2.0, PCI Express, SATA, DDR2 and HDMI is increasing as these standard interfaces are included in SOCs designed for applications such as single chip recordable DVD codec's and MP3 players. In order to stretch battery life of these SOCs, the semiconductor technologies require ultra-low power derivatives of high-performance logic manufacturing processes that enable production of very low-power SOCs for these mobile platforms and small form-factor devices. Today, many of these SOCs are manufactured in 90-nm process nodes, and the ramp for 65-nm design starts has been more aggressive than expected. The 45-nm process design is following close behind, with early versions of design rules and process parameters already available.
The challenge from the IP provider's viewpoint is to meet analog performance in a technology that has been targeted for densely packed digital logic. From the SOC integrator's perspective, the IP should be easy to integrate. The IP provider should have already dealt all of the details of creating the IP. The IP should also incorporate new circuit design techniques that accommodate lower supply voltages necessary for portable systems. At the smaller process nodes, design for manufacturing (DFM) must also be taken into account.
By Navraj S. Nandra. (Nandra is Director of Marketing for Mixed-Signal IP, Synopsys, Inc.)
Reprinted from SOCcentral.com, your first stop for ASIC, FPGA, EDA, and IP news and design information.