Power Has Consequences, So Chill Out!
Contributor: Envis Corp.
June 9, 2008 -- The March edition of Vanity Fair had an article that covered Google’s construction of a three-building data center next to the Columbia River in Oregon, to take advantage of cheap power no longer required by a defunct aluminum smelter. Apart from being a wonderful encapsulation of a smokestack industry giving way to high-tech, it is also an example of the transformation of where power is being consumed in the modern world.
In a data center, about 2/3 of the power is consumed in the servers and routers, and 1/3 is consumed in the air conditioning to get rid of the power dissipated uselessly as heat. But where is all that power actually used? While some goes into fans and disk drive motors, most of the power is consumed in semiconductors: the processors, memories and custom chips that make up the boards, that are packed in the racks, that constitute the electronic systems, that are packed into the buildings. As in any system, the power dissipated as heat is essentially waste. But it is expensive waste, since we need to use still more power to get it out of the building!
So the way we design chips for power is no longer simply something geeky of interest only to a few engineers in Silicon Valley; it has implications with major effects on the environment. In 2005, server farms consumed 15 gigawatts, or 1.2% of the entire US generating capacity. It has only grown since, as the number of servers and data centers continues to grow.
A few years ago, Patrick Gelsinger, Intel’s CTO, memorably pointed out that if we carried on designing semiconductors the way we were, then the power density on a processor chip would go way beyond a light-bulb to reach the same density as in a rocket nozzle. Since we would prefer that our laptops not scorch our desks, never mind that we occasionally want to actually use them on our laps, this is another reason that things have to change.
The large numbers involved, both in watts and dollars, mean that designers have to focus on making sure that their chips are designed to be as low power as possible. There are many approaches to this, spanning software, design tools, standards and process engineering, and today, power management is a critical aspect of EDA tool flows.
One of the most effective techniques used to reduce dynamic power of a design is clock gating. The concept behind clock gating is that if the contents of a register are not going to change on a clock cycle then it is better (i.e., consumes less power) to avoid clocking the register.
Current approaches to clock gating are bifurcated. Primitive approaches -- those embedded in today’s synthesis tools, or example -- don’t achieve enough power reduction. Manual approaches are very labor intensive, and dependent on the expertise of the designer. For a large block on an SOC, manual clock gating can result in months of work. For a heavily used microprocessor or other IP core, it can be years of work.
A next-generation approach to clock gating is required, one that is automatic and reduces both dynamic and static power. In effect, this means an approach that automatically manages the clock, to reduce dynamic power, at the same time as it reduces static power by reducing chip area, all without sacrificing chip performance.
Envis’ Chill embodies a new approach that combines an analysis and insertion software tool along with proprietary silicon elements that together shuts down many of the clocked elements. Chill runs in a few minutes to a few hours. This translates into lower development cost, due to the automatic insertion; lower manufacturing costs, due to the reduced area; lower packaging costs, due to the reduced static and dynamic power; and decreased battery usage in standby and active modes. Ultimately it produces a lower-power, higher-quality, more reliable design, faster.
Chill typically can achieve power reduction of up to 60% from the original design, or up to 30% from a netlist where a lot of manually inserted clock gating has already been done, through tightening the conditions on already gated elements and finding additional opportunities for gating. At the same time, it often reduces chip area by a few percent, and occasionally more, because of logic that has now been made redundant and which can be recovered by aggressive optimization.
Chill offers two sets of algorithms for clock gating. The first approach is a sophisticated combinational search and decision process about which elements to gate and what signals can be used or combined to effect the gating. The second approach is sequential, looking for conditions one or two clock cycles before that can be used to gate elements on subsequent clock cycles. This approach is especially powerful in heavily pipelined designs where disabling the clock to one stage on one clock cycle often means that the subsequent stage can be disabled on the following clock cycle.
Chill starts by partitioning the design into groups of sequential elements that can be enabled or disabled together (see Figure 1.).
In addition to reducing power, Chill reduces the design cycle. Typical projects spend between one and four months doing manual clock gating. Most manual clock gating can instead be automatically inserted by Chill in a few hours, saving the effort and the schedule delay of manually inserted clock gating. Instead of an iterative error-prone and lengthy process, Chill provides a correct-by-construction push-button solution.
In summary, managing to aggressive power budgets is becoming an even bigger problem than timing closure and meeting chip area goals. Envis’ Chill is a new approach to this problem, complementary to many other techniques such as power shutoff and voltage scaling. It uses patented fine-grained activity analysis to disable parts of the circuit transparently, reducing dynamic power without altering the functionality. At the same time, area is reduced which decreases static power due to leakage. Further, as a push-button process, it does all this quickly, removing the need for most of the long error-prone manual clock-gating phase of the design cycle.
Using tools like Chill and other power management techniques can make a significant reduction in the power that an individual chip produces. Multiplied by the billions of chips manufactured each year, this small individual savings scale to produce environmentally significant savings, removing the need for entire power stations with their accompanying pollution, greenhouse gases and long term effects.
By Paul McLellan, CEO, Envis Corp.
Paul joined Envis as CEO in November 2007 having previously worked part-time
as VP of marketing. Prior to joining Envision, Paul was VP of marketing at
Virtutech and VaST Systems, corporate VP of strategic technology at Cadence,
VP of engineering at Ambit (acquired by Cadence), and President of Compass
Design Systems (now a part of Synopsys). Earlier in his career he held
various positions at VLSI Technology and Compass Design Systems in both US
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