Japan Aerospace Exploration Agency Adopts Cadence Virtuoso IC 6.1 and Spectre Simulator
July 7, 2009 -- Cadence Design Systems, Inc. announced today that the Japan Aerospace Exploration Agency (JAXA) has adopted the Cadence Virtuoso IC 6.1 custom design platform and the Cadence Virtuoso Circuit Simulator. Building circuits that will be used in space exploration under extreme conditions without malfunctions requires the accurate modeling of multiple factors of disturbance, and then using those models to test the chip designs. JAXA determined that the Cadence Virtuoso technology is needed to develop such critical circuitry.
JAXA had been examining EDA products for its research and development department's designs, which include circuits that will be exposed to radiation in space that generates random noise and can result in circuitry malfunctions.
"It is critically important for JAXA to develop test LSIs to ensure that the devices will work in space," said Satoshi Kuboyama, Manager of Electronic Devices and Materials from Aerospace Research and Development Directorate, JAXA. "By using Virtuoso IC 6.1, we are able to predict behavior of circuits and verify many corner cases at one time, and development and experimentation time will be significantly reduced."
In addition to the Virtuoso technology's accuracy, reliability and ability to easily maintain and reuse IP, JAXA can take full advantage of tight integration between Virtuoso IC 6.1 and the Cadence Spectre circuit simulator. JAXA also adopted the Virtuoso Layout Suite XL for the necessary performance and accuracy to create design-rule-correct parts, minimizing overall design cycle time. The Layout Suite supports custom digital, mixed-signal and analog designs at the device, cell, and block levels. Its features include automation to accelerate custom block authoring, as well as Cadence space-based routing technology that automatically enforces 65/45-nm process and design rules during interactive and automatic routing.
Reprinted from SOCcentral.com, your first stop for ASIC, FPGA, EDA, and IP news and design information.