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IC Plus Standardizes Verification Process with Cadence Incisive SolutionNovember 27, 2009 -- Cadence Design Systems, Inc. today announced that IC Plus, a communication and networking IC design company in Taiwan, has adopted the Cadence Incisive verification solution with the Open Verification Methodology (OVM) and Cadence verification IP (VIP) to optimize development time while simplifying and standardizing its verification process. IC Plus has incorporated the Cadence OVM architecture and methodology into its SystemVerilog verification flow and significantly shortened its development time from months to only a few weeks. By adopting the Cadence solution, IC Plus standardized its verification process, improving production efficiency and predictability while achieving high-quality verification closure. The OVM, which Cadence co-created, comprises several advanced features, including interoperability, debugging, reusability and an easy-to-use verification model for testing. Its universal interoperability for SystemVerilog and reusable verification IP help facilitate the development and support of multi-language plug-and-play VIP. Debugging and reusability help maximize quality, productivity and predictability. The proven user-friendly model provides a simple platform for test creation. "For an IC design company like IC Plus, which has made great investments in R&D, the process of debugging is critical since it affects time and resources during the design process," said Albert Liu, R&D Vice President of IC Plus. "With the Cadence solution, we are able to not only set up a complete, automatic and systematic verification flow with less set-up time, but also to discover design bugs in the early stage, which in turn improves the quality of our products." | |
Reprinted from SOCcentral.com, your first stop for ASIC, FPGA, EDA, and IP news and design information. | |