STARC Adopts Incentia TimeCraft for Static Timing and Signal Integrity Analysis Solutions
December 15, 2009 -- Incentia Design Systems, Inc. today announced that the Japanese electronic design consortium STARC has validated Incentia’s TimeCraft static timing analysis (STA) and signal integrity (SI) analysis solutions and incorporated them into its STARCAD-CEL V3.5 Timing Signoff Flow.
STARCAD-CELV3.5 Timing Signoff Flow was defined by the consortium to address comprehensive signoff requirements in static timing and signal integrity analysis for 45-nm and below process technologies. TimeCraft met STARC’s requirements in general STA accuracy and functionality, location-based on-chip-variation (LOCV) analysis, cross-talk accuracy, and advanced signal integrity pessimism reduction. Moreover, TimeCraft demonstrated very fast runtime advantages in both single-thread and multi-thread flows that greatly shortened the analysis turnaround time for very big designs.
"The purpose of the STARCAD-CEL V3.5 timing signoff flow is to qualify the most efficient and comprehensive timing signoff solutions for STARC member companies," said Nobuyuki Nishiguchi, Vice President and General Manager, Development Department 1 at STARC. "Incentia’s TimeCraft was able to meet our signoff criteria in functionality and accuracy, and proved its fast runtime advantages for very big designs. We are pleased to incorporate TimeCraft into STARC V3.5 signoff flow, and provide our member companies with much improved productivity gains.”
Reprinted from SOCcentral.com, your first stop for ASIC, FPGA, EDA, and IP news and design information.