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Under the Lid: Analog Test Is Suddenly the Critical IngredientPublication: EDN Magazine January 7, 2010 -- ATPG (automatic-test-pattern generation), BIST (built-in self-test), and structural-test techniques have kept digital-test costs nearly constant during the explosion in digital complexity. Without these tools, however, as analog complexity starts to grow rapidly, analog-test cost is growing, too. "AMS [analog and mixed-signal] circuits account for 70% of SOC-test cost and 45% of test-development time, even though they make up a small fraction of the chip complexity," said Karim Arabi, senior director of engineering at Qualcomm, speaking at a panel on analog-IC test at the ITC (International Test Conference) in Austin, TX, last November. "There is no ATPG for AMS circuits. There is no practical fault model. And what DFT [design-for-test] and BIST efforts we use are purely custom." Arabi’s complaint neatly summarizes the situation. By Ron Wilson, EDN Executive Editor | |
Reprinted from SOCcentral.com, your first stop for ASIC, FPGA, EDA, and IP news and design information. | |