An Easy Way to Adopt Statistical Timing Analysis and Do Better Designs
Contributor: Extreme DA
January 21, 2010 -- Why should IC designers adopt statistical analysis? There are several drivers for this. The first is that silicon nodes are continuing to move to smaller geometries where variations in device performance and interconnect delay are more dominant factors. The trend in 2010 will be for leading-edge fabless semiconductor companies to move to the 32-nm node or even directly to 28nm. Greater unpredictability means design success is harder to achieve. Figure 1 dramatically illustrates the statistical effects at the 40-nm node with up to a 40% variation in timing.
The call to adopt statistical analysis has been heard by the semiconductor industry. Design executive Ana Hunter, Vice President of Technology, Samsung Systems LSI Foundry Group, has said, "We have been working on statistical timing analysis [STA] for quite a while now. We have concluded that it's just about a must at 45nm, and definitely necessary at 32nm." Now that foundries see it as an essential practice, design teams will be expected to follow.
The second driver is the need for a new tool-flow. Existing timing sign-off methods have been successful based on the assumption that the foundry can control the variation and yield in manufactured silicon. Given that assumption is no longer accurate, the current timing sign-off methods that rely on doing a timing analysis at multiple operating modes and corners (process, voltage, temperature, power-level) is starting to break down. A design with over 40 mode+corner combinations is typical for a modern IC targeted for a mobile product with its requirements for long-battery life and low-power operating modes. Underlying the use of corner-based methods is the assumption that sufficient guard-bands or pessimism in the modeling and the timing analysis stages will 'guarantee' a working design. While over-design is an option, it ignores the competitive pressures to build a faster, lower-power and smaller silicon chip than another IC vendor, and essentially takes a new design back to an earlier generation silicon node. And finally, these pessimistic, over-constrained designs, surprisingly can still fail in production silicon because the outliers have not been analyzed.
Statistical analysis is different and shows the sensitivities for all paths in a design to the effects of variation in just a single run. With the right tool and models, it is easy to find those outlying nets and paths that have the highest sensitivity and are most likely to have timing failure.
The costs and challenges of statistical timing analysis
Okay, if the time has come for using statistical timing analysis, what is the cost of adoption? What are the challenges? The foundation for statistical timing analysis is to use models of the variation in both the cells and the interconnect so the analyzer can take advantage of it. The task of creating a new kind of cell library is compute-intensive and can take 10X longer than traditional cell characterization. Since cell characterization is already a bottleneck for design teams because of the need for many Spice simulations, managers are understandably reluctant to add further delays in model creation. Companies such as Altos Design Automation are attacking this area with new high-speed characterization methods, but the increased overhead remains. Statistical analysis also requires significantly more computation than a traditional timing analysis. Fortunately, this is off-set by new multi-threaded analysis methods that speed analyzer run-times.
Even though a full statistical timing analysis delivers the most accurate and complete solution for addressing manufacturing and environmental variation, there are alternatives that incorporate variations in analysis but do not require re-characterization of cell libraries. A popular method uses a derating factor applied globally to all the paths in a design and is called OCV (on-chip variation). Applying OCV factors globally does change the margins in the design but can easily make paths either too optimistic or too pessimistic. Figure 2 illustrates the compromise of this approach which will not prevent timing failures or over-design.
Local OCV (LOCV) is a methodology that provides a derating factor based on path depth and/or relative location of the cells that make up the path. Some implementations in the marketplace take short cuts and ignore derating factors for arcs. In particular, the length and number of cells in a path should be accounted for, since long paths tends to reduce variation to a statistical mean. And long paths are more likely to use more of the timing budget.
To make the distinction clear, the term "parametric OCV" (POVC) will be used for a complete and correct implementation of the LOCV approach. It has the advantages of modeling OCV statistically to reduce pessimism without library re-characterization. This is attractive to design teams who use a corner-based methodology and want to see a graphical statistical analysis for sensitive critical paths in a design.
A detailed comparison with the use of a statistical library is shown in Table 1. The POCV approach can approximate much of the analysis of full SSTA with the exceptions of slew/load dependency and interconnect variation.
To control the variation parameters used in a POCV analysis, the deltas in cell delays and capacitance and resistance values are defined in terms of percentages of nominal values. This means that cumbersome delay tables are not necessary. The delay distributions are propagated through the design and take into account advanced physical analysis such as same and different transitions in clock reconvergence pessimism removal (CRPR). Figure 3 illustrates how statistical timing delay is calculated.
Because random cell variation tends to statistically cancel itself over long paths, pessimism is reduced in the POCV approach compared to methods using just global variation and derating parameters.
The drivers for better variation analysis have created new solutions for doing statistical analysis. With a POCV flow that addresses variation on all timing paths in cells including path length, depth and slew/load points, needless pessimism and guard-banding can be eliminated. With zero-setup cost for library modeling and multi-threaded timing analysis, the cost of adoption is low. Designers can use a staged approach to introduce statistics, like random cell variation, and keep other elements of a more traditional flow. And finally, by specifying variations as percentages on some key parameters, statistical analysis makes minimal changes to existing tools scripts and design flows.
Design teams are understandably reluctant to adopt new design flows or methodologies, and might be tempted to continue to stay with traditional corner analysis in the hope their foundries can control manufacturing processes as they adopt newer process nodes. The companies that move to statistical timing analysis now before being forced to abandon traditional corner analysis will be well positioned to rollout full statistical methodologies where there are no alternatives. Design teams that postpone will have to implement a new methodology at the same time they are rolling out a new process technology. This is an inflection point of change in the design that will be disruptive. And it is very likely a new design tool-set will be needed and cause further disruptions. The burden on design and methodology engineers to do all three changes simultaneously will jeopardize technology ramp-up and product success. Staged adoption of statistical timing analysis today will continue to pay-off for years into the future, and introducing techniques like POCV into existing design flows can minimize the disruption so often associated with breakthrough capabilities.
By Ruben Molina.
Ruben Molina is Director of Technical Marketing at Extreme DA. Before Extreme DA, Molina held senior design management positions at LSI Logic. He holds a B.S. in Engineering and an M.S.E.E. from CSU, Los Angeles. He is an author of five U.S. Patents.
Reprinted from SOCcentral.com, your first stop for ASIC, FPGA, EDA, and IP news and design information.