How to Make Virtual Prototyping Better than Designing with Hardware: Part 2 - The Importance of Testability In Virtual Prototyping
Publication: EE Times Embedded
June 23, 2010 -- Virtual prototypes are much more conducive to design automation because the environmental stimulus is just another component of the simulation. Careful control of the stimuli results in deterministic behavior of the product simulation. Sometimes tool integrations are still required (for example a debugger, Matlab or LabView), but complexity is reduced to the exchange of information via control APIs and configuration files rather than cables, networks, and manual setup of test panels.
Users of VP prototypes are able to automate the testing process via software scripts eliminating the need for custom equipment and cables. Flash memory is simply loaded with a program image rather than re-flashed with complicated tools on the real hardware. Finally, the virtual prototype is truly time share-able as each user can have their custom configuration without fear of breaking anothers test setup.
By Everett Lumpkin and Casey Alford. (Lumpkin is Senior Function Design Methodology and Automation Engineer with Delphi Corp. and Alford is the Director, Field Engineering & Technical Services with Embedded Systems Technology.)
Reprinted from SOCcentral.com, your first stop for ASIC, FPGA, EDA, and IP news and design information.