Parametric yield: Do You Know What You Miss?
Publication: EE Times EDA Designline
November 10, 2010 -- Since moving to sub 65-nm technologies, pre-defined corners (PDC) verification has attained its limits. The number of corners to verify has become huge with always the possibility of over-design. The worst is that these corners cannot guarantee the design. Some corners could fall inside the process parameters space while others do not really need to be tested.
In this context, EDA has started looking for solutions for this new and key concern. Many solutions have been developed on the back-end side to reduce variability, analyze yield or enhance it. These solutions, although very useful, were not sufficient. Another effort at design level has been made concerning parametric yield. This is thoroughly developed in this article.
Today, the EDA market offers tools based on the following different approaches:
From the different approaches, two main workflows appear:
By Yoann Courant and Firas Mohamed. (Mohamed is founder, chairman of the board and CEO of Infiniscale SA and Courant is cofounder and R&D director of Infiniscale SA.)
Reprinted from SOCcentral.com, your first stop for ASIC, FPGA, EDA, and IP news and design information.