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Introduction to SVA Assertions for Design EngineersPublication: Design & Reuse March 10, 2011 -- Assertions and assertion-based verification (ABV) are a hot topic, but many engineering teams remain unfamiliar with the benefits that assertions bring to the design and verification process. This article discusses the rationale for using assertions, the benefits of using assertions throughout the design and verification process, and a step-by-step approach to implementing assertions within a design. This article is written from the viewpoint of a design engineer. Hopefully both design and verification engineers will see the relevance of (and humor in) these comments from the designer-centric world view.
By Eric Deal. (Deal is with Cyclic Design, LLC.) | |
Reprinted from SOCcentral.com, your first stop for ASIC, FPGA, EDA, and IP news and design information. | |