Silicon Labs Addresses Optical Networking Challenges with High-Performance 4-PLL Clock ICs
May 11, 2011 -- Silicon Laboratories, Inc. today introduced the industry's highest performance, most integrated clock ICs available to address the complex timing requirements of high-speed optical transport network (OTN) applications. Leveraging Silicon Labs' patented DSPLL technology, the new Si5374 and Si5375 clocks are the first single-chip timing ICs to integrate four independent, high-performance phase locked loops (PLLs), providing twice the PLL integration and 40% lower jitter than other solutions.
OTN applications pose complex timing challenges by requiring multiple low-jitter clocks at non-integer-related frequencies. Silicon Labs' quad-DSPLL Si537x devices produce up to eight low-jitter output clocks, simplifying the design of any-protocol, any-port 10G, 40G and 100G OTN line cards.
Each DSPLL clock multiplier can be configured to generate any frequency from 2kHz to 808MHz from a 2kHz to 710MHz input. This exceptional frequency flexibility reduces the cost and complexity of multi-protocol OTN line cards by minimizing the need for multiple jitter-cleaning clock ICs. The Si537x devices' flexible DSPLL architecture simplifies the generation of high-speed PHY reference clocks with industry-leading jitter performance of 0.4ps, eliminating the need for discrete VCXO-based PLLs currently used in OTU3 and OTU4 applications.
The Si537x devices can reliably lock to gapped clock inputs — a critical OTN line card clock requirement — without separate upstream low-bandwidth PLLs. Other carrier-grade features include SONET-compatible jitter peaking (0.1dB max) and a hitless switching capability that minimizes output clock phase transients during reference switching, producing a 25Xx smaller phase transient than other solutions. Each DSPLL engine features a fully integrated loop filter that supports user-programmable bandwidths as low as 4Hz, enabling wander filtering in addition to jitter attenuation, configurable on a per channel basis.
"The convergence of high-bandwidth data, video and voice services over OTN and increasing optical line card port densities require higher levels of clock integration and ultra-low jitter to minimize design cost and complexity," said Mike Petrowski, General Manager of Silicon Labs' timing products. "Silicon Labs' new Si537x clock ICs offer more high-performance PLL integration than competing solutions at the industry's lowest jitter levels, setting a new benchmark for purpose-built OTN clocking solutions."
The Si5374 device has eight input clocks and eight output clocks while the Si5375 offers four input clocks and four output clocks for applications requiring fewer clocks. With its quad-DSPLL configuration, a single Si5374 clock can generate different frequencies simultaneously, enabling the design to support SONET/ SDH, 1/ 10/ 100G Ethernet, 1/ 2/ 4/ 8/ 10G Fibre Channel, 3G/ HD SDI video and other protocols simultaneously in the same device.
The Si537x clocks provide a smooth upgrade path for existing users migrating from Silicon Labs' Si5319/ 26 jitter-attenuating clocks to a more integrated jitter-cleaning clock solution designed to minimize BOM cost and complexity. The Si537x clocks effectively replace four timing devices with a single IC in high-port-count 10G/ 40G/ 100G OTN line cards.
Availability and Pricing
Samples and production quantities of the Si537x clock ICs are available now. Si537x clock prices range from $39 to $59 in 10,000-unit quantities. The Si5374-EVB and Si5375-EVB evaluation kits are available for $350 each.
Reprinted from SOCcentral.com, your first stop for ASIC, FPGA, EDA, and IP news and design information.