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Veridae Systems and Dini Group Team to Accelerate ASIC Verification with a Multi-FPGA Prototyping and Debug SolutionJune 8, 2011 –– Veridae Systems, Inc. and the Dini Group, Inc. have combined Veridae's Certus FPGA Prototyping Suite with the Dini Group's prototyping and I/O hardware to deliver a complete platform for multi-FPGA prototyping and debug. FPGA-based ASIC prototyping is challenging in many regards with the most time and effort spent in debug. Conventional approaches require long, repeated cycles of instrumentation, synthesis, followed by FPGA place-and-route. Certus reduces this time by offering a debug platform that encompasses a single, synchronized view of a complex ASIC design. And Certus effortlessly handles this task across multiple FPGAs and multiple clock domains. Signal selection and high-speed troubleshooting is performed without the time intensive cycle of instrumentation/ synthesis/ FPGA place-and-route. As a result, engineers can quickly pinpoint unexpected behaviors, correct problems, and rapidly move an ASIC prototype into first mask success. Certus runs on Dini boards with one to twenty FPGAs, and designs of up to 130 million ASIC gates can be run at, or near the target silicon speed. All common interfaces are accommodated, and daughter cards provide custom user requirements. The combined solution offers incredible cost savings over traditional methods and speeds time to first silicon. The Certus Suite for FPGA prototyping provides a single, fully synchronized and aligned waveform view across all FPGAs and clock domains. Furthermore, Certus can be tightly coupled with your software debugger to accelerate FPGA-based system validation and debug. The Certus suite is based on Veridae's proven set of software tools that include the Implementor for semi-automated instrumentation of your design; the Analyzer for configuration and capture; and the Investigator for data expansion through signal interpolation. AvailabilityCertus is available now from Veridae Systems, and the company will support users implementing the suite on a Dini Board to establish an optimal FPGA prototyping and debug solution. | |
Reprinted from SOCcentral.com, your first stop for ASIC, FPGA, EDA, and IP news and design information. | |