Synopsys Delivers Unified Solution for Digital and Custom SOC Designs
September 26, 2011 -- Synopsys, Inc. today announced advances in its Galaxy implementation platform with the availability of its unified solution for mixed-signal designs. The new unified solution provides seamless integration between IC Compiler physical implementation and the Galaxy Custom Designer solution, allowing design teams to easily move between digital and custom implementation flows while maintaining design data integrity. The unified solution accelerates the design development cycle by enabling quick and reliable custom edits to IC Compiler designs at any stage of development, including the time-critical tape-out phase. "To manage complexity and reduce the development times of our mixed-signal designs, we need a unified methodology for digital and analog implementation," said Didier-Jerome Martin, Physical Implementation Manager at STMicroelectronics' Microcontroller Division. "Using Synopsys' unified physical-implementation solution on a 32-bit microcontroller design we reduced the cycle time by 25 percent from initial floorplanning to final tape-out, as compared to our previous flow. We also experienced a 2X productivity gain when performing late-stage layout ECOs, at a time in the project when schedules were compressed and time was at a premium."
The new unified IC Compiler and Custom Designer solution provides a powerful capability to perform custom editing of IC Compiler designs throughout the physical-implementation flow, including floorplanning, placement, clock tree synthesis, routing and chip finishing. Virtually no setup is required, and the loss-less, multi-roundtrip capability gives users a high degree of flexibility to make custom edits to the design while ensuring that all changes are reflected back into IC Compiler.
IC Compiler users can now take advantage of Custom Designer's advanced productivity features such as SmartDRD technology for design-rule-driven layout, interactive point-to-point auto-routing, and automation technologies such as auto-bus and auto-via generation. All this comes with push-button access to the same IC Validator physical verification and StarRC parasitic-extraction tools used with IC Compiler, providing designers with a unified physical implementation solution.
"Designing today's digital and mixed-signal SOCs involves multiple iterations between digital and custom implementation," said Bijan Kiani, Vice President of Product Marketing at Synopsys. "The new innovations in the Galaxy Platform provide the capabilities needed by design teams to manage the increased complexity and aggressive development schedules of complex mixed-signal designs."
Synopsys will premiere a webinar entitled "Use IC Compiler and Custom Designer to Shave Weeks Off Your SOC Development Cycle" on October 19, 2011 at 10:00a.m. (PT) that will showcase the seamless integration between IC Compiler and Custom Designer. Visit www.customdesigner.com to view a video demonstration and learn more about the IC Compiler and Custom Designer solution.
Reprinted from SOCcentral.com, your first stop for ASIC, FPGA, EDA, and IP news and design information.