 |
|
Density Requirements at 28nmPublication: EE Times EDA Designline March 12, 2012 -- In recent discussions with customers around the world, we have been hearing a surprising new message; that, at 28nm, they have to care about density at the cell-design level "like never before." It's surprising because density has historically been a manufacturing issue that was handled post tape-out or during chip assembly. However, where and how density is handled in the design process has evolved significantly along with the process technologies. In this article, I'll take a look at how density has evolved from a back-end manufacturing issue that was of little interest to designers to a design concern that affects the layout of standard cell libraries.
By Joe Davis. (Davis is Product Manager for Calibre interactive and integration products at Mentor Graphics Corp.) | |
Reprinted from SOCcentral.com, your first stop for ASIC, FPGA, EDA, and IP news and design information. | |