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DFI Technical Group Releases Version 3.1 of Its High-Speed Memory Controller and PHY Interface SpecificationMay 29, 2012 -- The DFI Technical Group today released the DFI 3.1 specification, the latest version of the industry specification that defines an interface protocol between DDR memory controllers and PHYs. The specification enables the development of systems-on-chip (SOCs) that support the DDR3 and DDR4 memory standards. Version 3.1 adds support for the LPDDR3 mobile memory standard for smartphones and tablets, as well as enhancements to the low-power interface and training features. The preliminary DFI 3.1 memory specification is available now for download from the DFI website. | |
Reprinted from SOCcentral.com, your first stop for ASIC, FPGA, EDA, and IP news and design information. | |