Integrand Enables RF IC Design Solution for GlobalFoundries' 40-nm LP Technology
June 4, 2012 -- Integrand Software, Inc. and GlobalFoundries today announced the availability of a comprehensive solution for RF IC design on GlobalFoundries' 40-nm-LP technology. GlobalFoundries' RF solutions flow enables a designer to optimize inductors using Integrand's Optimum Inductor Finder (OIF) inductor synthesis tool. The flow works within the Cadence Virtuoso environment.
The OIF technology deployed by GlobalFoundries was developed using Integrand's EMX EM simulator and Continuum model-generation tool. GlobalFoundries has done extensive verification of the models and confirmed that they show very close correspondence to silicon measurements.
"Integrand's EMX and Continuum software create true scalable models for passive components like inductors," said Dr. Sharad Kapur, President of Integrand Software. "The associated OIF enables a designer to find optimal components in a matter of seconds without resorting to third-party synthesis tools or from list based search approached."
Integrand's OIF, a GUI-based analog-synthesis tool, is now deployed within the PDK to let GlobalFoundries customers enter their desired inductances and make trade-off decisions between maximum Q, minimum area. Furthermore, the Spice model parameters are geometric so as to allow EDA layout parasitic extraction (LPE) tools to extract model parameters to do post layout simulation.
"GlobalFoundries uses Integrand's EMX and Continuum to characterize and simulate passive devices. The tools facilitate virtual fabrication and automatic construction of accurate scalable inductor models with good model-to-hardware correlation," said Michael Cheng, Senior Director at GlobalFoundries. "These inductor models are then integrated into an Optimum Inductor Finder (OIF) which is released through GlobalFoundries' RF Design Kit. The OIF offers circuit designers the flexibility to synthesize inductor designs specific to their needs."
Reprinted from SOCcentral.com, your first stop for ASIC, FPGA, EDA, and IP news and design information.