Magma's Blast Create RTL Synthesis Solution Validated by IBM ASIC
January 12, 2004 -- Magma Design Automation Inc. (Nasdaq:LAVA - News), a provider of chip design solutions, today announced that IBM Microelectronics is accepting design data from Blast Create, Magma's high-capacity synthesis tool based on the FixedTiming methodology, for implementation of ASIC designs. Designs validated by IBM's ASIC methodology group have shown the handoff from Blast Create to provide a high degree of correlation with IBM's static timing tool, Einstimer(TM), a part of IBM's physical design system, Chip Bench.
"We qualified Magma's Blast Create by accepting multiple test cases synthesized by Magma, and successfully transferred them into our ASIC design system," said Maurice Kinney, synthesis methodology engineer at the IBM Technology Group. "This provides our customers additional synthesis tool choices for implementing ASIC designs."
"Blast Create's gain-based synthesis and FixedTiming methodology, combined with its very high capacity and fast turnaround time, improve quality of results (QoR) in complex SoCs -- area, performance and power improve by 5 percent to 15 percent," said Nitin Deo, vice president of product marketing for Magma. "Conventional approaches to logic design require partitioning and delay budgeting of the design into blocks with fewer than 250,000 gates. For today's 10 million-gate and larger SoC designs this requires too many blocks to be integrated at the top level -- making chip-level timing convergence unpredictable -- and it causes many layout-to-synthesis iterations.
"IBM's qualification of Blast Create is the latest sign of increasing adoption of Magma's synthesis as a production-proven technology. This ongoing shift in ASIC design will reduce overall development time for ASIC designers."
Blast Create offers all aspects of front-end design: RTL synthesis, datapath synthesis, physical synthesis, DFT analysis and scan insertion, static timing analysis and Tcl-based scripting environment. Both popular hardware definition languages (HDLs), Verilog and VHDL, are supported. Blast Create accepts design constraints in SDC format and libraries in .lib format, avoiding the need for and cost of adapting Blast Create to existing logic design environments.
Reprinted from SOCcentral.com, your first stop for ASIC, FPGA, EDA, and IP news and design information.