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 Category: FPGAs/PLDs/CPLDs & Structured ASICs: Tuesday, May 21, 2013
 FPGAs/PLDs/CPLDs & Structured ASICs

Recent FPGA/PLD/CPLD
& Structured ASIC News


All Technology & Product News since Tuesday, April 23, 2013


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The so-logic FPGA database is a free directory of FPGA families from manufacturers such as Xilinx, Altera, Actel, Cypress, Lattice, QuickLogic, SiliconBlue with their devices and majority of the data for each device. You can see here a complete PLD architecture: logic cells, embedded memory, clock resources, dsp blocks, IPs, I/O blocks, configuration bits and a list of available packages for each device. The database also contains a parametric search engine, but registration is required to use this search feature.

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Most-Read Recent News (updated daily)
•eMemory Announces NeoFuse Anti-Fuse eNVM Technology
•FishTail Design Automation Joins Cadence Connections Program
•Altera to Acquire Enpirion
•Altium Updates Designer 13.2 to Enhance Design Clarity and Reduce Supply-Chain Risk
•Si2 Celebrates Its 25th Anniversary with Complimentary Lunch and Evening Reception During DAC
•Energy-Efficient EFM32 Wonder Gecko with ARM Cortex-M4 and FPU Now Available
•TI Delivers ZigBee SOC with an ARM Cortex-M3 MCU
•Chip Memory Technology Emerges from Stealth Mode to Reveal New Embedded NV Memory Solution
•Elecard Releases New Version of Elecard ARM Codec SDK
•UltraSoC Delivers Universal Debug IP to PMC-Sierra
•HiSilicon Technologies Tapes Out 50+ Million Instance ARM Processor-based SOC Using Synopsys IC Compiler
•Ultra-Low Latency H.264 Video Encoding Now Available from CAST
•Management Day at DAC to Discuss the Trade-Offs Involved in Modern SOC Design
•New Power ISA 2.07 Now Available from Power.org
•Cadence Introduces the Tempus Timing Sign-off Solution

SOCcentral has abstracted and indexed a large number of articles, tutorials, white papers, etc. on both FPGAs/CPLDs/PLDs and Structured ASICs that are available online. Scroll down to see the list of Magazine & Journal articles on FPGAs or Structured ASICs, as well as a list of Tutorials, White Papers, etc. on FPGAs or Structured ASICs that we've identified.


Designer's Mall

Suggested Tutorials, Whitepapers & Application Notes

More SOCcentral news articles on FPGAs/CPLDs/PLDs (4 to 12 weeks ago)

Altera Announces Availability of Cyclone V SoC Development Kit (4/22/2013)
DVClub Presentations Highlight Important Data from Hardware-Verification Industry (4/22/2013)
frobas Chooses SpyGlass CDC for SOC Design Flow (4/22/2013)
CEVA Introduces Android Multimedia Framework for Energy Efficient Multicore Systems (4/18/2013)
Imagination's PowerVR VXE Multi-Standard Video-Encoder IP Now Supports VP8 (4/18/2013)
Joe Costello Shares His Secrets for Communicating a Compelling Company Story (4/18/2013)
Andes Technology Unveils New Ultra-Efficient Processor Core for Low-Power Applications (4/17/2013)
ARM and Arteris Extend Partnership to Deliver Additional Interconnect Options (4/17/2013)
ARM Introduces New License Model for Big.Little Technology (4/17/2013)
Avnet Electronics Marketing Launches AXIOM Magazine for Americas Design Community (4/17/2013)
Accellera Systems Initiative Announces Standard for Tracking Soft IP Use (4/16/2013)
Arasan Chip Systems Announces First SD 4.1 Total IP Solution (4/16/2013)
Flexras Technologies Enhances Wasga Compiler Partitioning Tool (4/16/2013)
Aldec Presents VHDL Testbench Webinar (4/15/2013)
Altera Acquires TPACK to Expand OTN Solution Capabilities (4/15/2013)
Altera and AppliedMicro to Cooperate on Joint Solutions for High-Growth Data Center Market (4/15/2013)
Altera and TSMC Collaborate on 55-nm EmbFlash Process (4/15/2013)
Annual SoCIP Conference Opens for Registration (4/15/2013)
Dolphin Integration Introduces Complete IP Offering for Power-Metering Applications (4/15/2013)
Evatronix Enhances Its MIPI SLIMbus Device IP with New Customization Options (4/15/2013)
International System-on-Chip (SoC) Conference Calls for Speakers and Sponsors (4/15/2013)
Microsemi Achieves NIST Certification on EnforcIT Cryptography IP Cores for FPGA and ASIC Designs (4/15/2013)
Altera Demonstrates QPI 1.1 FPGA Home Agent for Enhanced Server Capabilities (4/10/2013)
Cypress' New PSoC Creator 2.2 IDE Delivers New Components, Easy Component Distribution and Custom Documentation (4/10/2013)
Cypress's New $25 PSoC 4 Pioneer Kit Available for Pre-Order from Premier Farnell (4/9/2013)
GrammaTech Helps EEMBC Ensure Robustness of Processor Benchmarks (4/9/2013)
Altera Demonstrates 32-Gbps Transceiver with Leading-Edge 20-nm Device (4/8/2013)
intoPIX Launches New Ultra-Compact JPEG2000 FPGA IP Cores (4/8/2013)
Mentor Graphics Delivers Simulation and Emulation Solutions to Verify Serial Attached SCSI Products (4/8/2013)
Mentor's Harry Foster to Present Functional Verification Study at April 8th DVClub (4/8/2013)
Xilinx Enables OEMs to Develop Smarter Broadcast Solutions with Availability of Its Real-Time Video Engine 2.1 (4/8/2013)
Xilinx Vivado Design Suite Accelerates Time-to-Integration and System-Level Design (4/8/2013)
Mentor Graphics Announces the First IP-to-System, UPF-based Low-Power Verification Solution (4/4/2013)
Accellera Systems Initiative Launches Working Group to Standardize Interoperability of Multiple Language Verification Environments and Components (4/3/2013)
Xilinx Vivado Design Suite Accelerates Time to Integration and System-Level Design (4/3/2013)
Digital Core Design Unveils New I2C Bus-Interface Core (4/2/2013)
GSA to Host 2013 GSA Silicon Summit (4/2/2013)
Real Time Logic Secures ASIC-Powered Devices M2M Applications (4/2/2013)
EDA Consortium Reports Revenue Increase for Q4 2012 (4/1/2013)
Algo-Logic Systems Launches Second-Generation Ternary Search Engine Solutions for the New Tabula ABAX2 P-Series of 3PLDs (3/27/2013)
ASSET InterTech Enhances IJTAG Embedded Instrumentation Tool for Debugging SOCs and Testing Circuit Boards (3/27/2013)
OCP-IP Releases OCP Debug Socket Specification 2.0 (3/26/2013)
Tabula Releases New EDA Technologies in Support of Its Suite of High-Performance Packet-Processing Solutions (3/26/2013)
Tabula Sets New Benchmarks with a Suite of 100G Programmable Solutions Based on Its ABAX2 P-Series of 3PLDs (3/26/2013)
INRIA and Kalray Strengthen Their Scientific Collaboration on the MPPA Manycore Processor and Parallel Computing (3/25/2013)
Microsemi Integrates Inicore Enhanced Reliability CAN IP into SmartFusion2 SoC FPGA (3/25/2013)
Synopsys Speeds Timing Closure with Advanced Sign-Off-Driven ECO Guidance (3/25/2013)
Truechip Solutions Partners with Avant Technology to Market Verification IP Products in Asia (3/25/2013)
Cypress's PSoC 4 Architecture Delivers the Most-Flexible, Lowest-Power ARM Cortex-M0-Based Devices for Embedded Designs (3/20/2013)
Accellera Systems Initiative Completes SystemC AMS 2.0 Standard (3/19/2013)
Tensilica Joins HSA Foundation to Help Establish Standards for Embedded Heterogeneous Computing (3/19/2013)
Xilinx Extends its Zynq-7000 All Programmable SoC Family to Combine the Highest-Performance ARM Processor-based Analytics, Control and Signal Processing (3/19/2013)
Altera Cyclone V GT FPGA Achieves Compliance for PCIe Gen2 at 5Gbps (3/18/2013)
Arasan Chip Systems Announces New Channel Partner in India (3/18/2013)
Blue Pearl Software Adds STARC Support to Further FPGA RTL Sign-Off (3/18/2013)
Chips&Media Extends CODA9 Series with AVS+ Chinese New Video Standard (3/18/2013)
Tektronix Demonstrates MIPI Alliance M-PHY Test Solution with Synopsys Silicon-Proven HS-Gear3 M-PHY IP (3/18/2013)
HDL Design House Announces PCS IP Core (3/12/2013)
Cadence Announces First Commercially Available Design IP and Verification IP for Mobile PCI Express (3/11/2013)
Cadence to Acquire Tensilica (3/11/2013)
Carbon Expands Embedded Systems Offerings with Performance Analysis Kit Featuring the ARM Cortex-R7 Processor (3/11/2013)
Digital Core Design Announces DuART tiny UART IP Core (3/11/2013)
Lattice Announces Smallest FPGA for Miniature Systems (3/11/2013)
MathWorks Announces Release 2013a of the MATLAB and Simulink Product Families (3/11/2013)
Carbon Announces Carbon Performance Analysis Kit Featuring the ARM Cortex-R7 (3/5/2013)
Lumagen Announces First Radiance Video Processor with Integrated Darbee Visual Presence Technology (3/5/2013)
Solarflare Accelerates Development of Custom, FPGA-Based Applications with Availability Firmware Development Kit for ApplicationOnload Engine (3/5/2013)
Avant Technology to Represent Recore Systems' IP Products in Asia (3/4/2013)
Real Intent Signs Grand Technology as Distribution Partner for Taiwan (3/4/2013)
Revised IEEE 1800 Standard Intended to Improve Efficiency of Electronic-System Design and Verification (3/4/2013)
Xilinx Solutions Target Growing ASIC and ASSP Gaps for Next-Generation Smarter Networks and Data Centers (3/4/2013)
ARM Mali GPUs Submitted for OpenGL ES 3.0 Conformance (3/1/2013)
PLDA and ReFLEX CES Announce New Line of System-on-Module (SoM) Products (2/28/2013)
AM3D Audio Enhancement Ported to Tensilica's HiFi Audio DSPs (2/27/2013)
Cadence Rolls Out 2013 CDNLive User Conferences (2/27/2013)
Oasys Design Systems Expands into South Korea (2/27/2013)
VLSI Plus Offers Multiple Video Source MIPI CSI2 Transmitter IP Core (2/27/2013)

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Magazine & Journal articles on FPGAs/CPLDs/PLDs

The Power of Developing Hardware and Software in Parallel (Design & Reuse) 5/2/2013
Boost DFT Efficiency for Large SOCs (Test & Measurement World) 4/23/2013
Using Audio Codec IP as the Digital Audio Hub in Mobile Multimedia Systems (EDN Magazine) 4/23/2013
FPGAs Offer Cost-Effective, Flexible Solutions for Remote Radio Heads (EE Times Programmable Logic Designline) 4/18/2013
3D-IC Integration: A Stepwise Approach (Tech Design Forum) 4/17/2013
Complex Standards Demand New Approaches to IP Quality (Chip Estimate Corp.) 4/16/2013
Stitch and Ship No Longer Viable (EE Times EDA Designline) 4/15/2013
Increased Functional Safety Is a Must Have in Networked Embedded Designs (EE Times Programmable Logic Designline) 4/11/2013
Advances in EDA Design Methodologies Led by Next-Generation FPGAs (DSP-FPGA) 4/10/2013
SOC FPGAs Combine Performance and Flexibility (EDN Magazine) 4/10/2013
Time to Take Up the 3D-Integration Challenge (Tech Design Forum) 4/10/2013
Small-Scale Programmable Logic Devices Offer Numerous Benefits (New Electronics Magazine) 4/9/2013
SSM Policy-Driven System Management Updates SOC Architecture to Meet Today's Operation Complexities (Chip Estimate Corp.) 4/9/2013
Building Your UVM Verification Environment for Cache-Coherent Interconnects (Design & Reuse) 4/4/2013
Extreme Code Density: Energy Savings and Methods (Chip Estimate Corp.) 4/2/2013
FPGAs Supercharge Instrument Flexibility (EE Times Programmable Logic Designline) 4/1/2013
Communication-Centric Test and Debug Infrastructure for Multicore SOCs (Design & Reuse) 3/28/2013
Using Parallel FFT for Multi-Gigahertz FPGA Signal Processing (EE Times Test & Measurement Designline) 3/28/2013
How FPGAs Are Breathing New Life into the Analog Video Format (EE Times Programmable Logic Designline) 3/21/2013
The Challenges of Using Open-Market IP in ASIC Designs (Chip Estimate Corp.) 3/19/2013
Hardware (and Software) Implications of Endianness in SOC Design (Embedded.com) 3/17/2013
Tensilica Acquisition to Accelerate Cadence Core Strategy (Electronic Engineering Times (EE Times)) 3/13/2013
The Coming Impact of Mobile PCI Express (M-PCIe) on SOCs and Devices (Chip Estimate Corp.) 3/12/2013
Design Transition from Sync to Async: Design and Verification Challenges (Design & Reuse) 3/11/2013
Virtual Prototyping Methodology to Boot Linux on the ARM Cortex A15 (EE Times EDA Designline) 3/11/2013
Virtual Prototyping Methodology to Boot Linux on the ARM Cortex A15 (EE Times EDA Designline) 3/11/2013
Optimizing Clock-Tree Distribution in SOCs with Multiple Clock Sinks (Embedded.com) 3/10/2013
Analyzing the Options in High-Bandwidth System Interconnect (Altera Corp.) 3/8/2013
An Introduction to Off-Loading CPUs to FPGAs: Hardware Programming for Software Developers (EE Times Programmable Logic Designline) 3/7/2013
Best Design Practices for High-Capacity FPGA Devices (Electronic News) 3/4/2013
Prototyping Signal Processing and Communications Algorithms on FPGAs Using Model-Based Design (Electronic News) 2/27/2013
State of RTL-based Design: Is It Time to Move Beyond? (Design & Reuse) 2/25/2013
Using 3rd-Party IP in ASIC/SOC Design (EE Times EDA Designline) 2/25/2013
FPGA Design Heads into the Cloud (EE Times Programmable Logic Designline) 2/22/2013
Designing Low-Power Video Image Stabilization IP for FPGAs (EE Times Militray & Aerospace Highlights) 2/19/2013
Guidelines for Early Power Analysis (EE Times EDA Designline) 2/11/2013
Implementing Analog Functions in Rugged, Rad-Hard FPGAs (EE Times Militray & Aerospace Highlights) 2/11/2013
The Perfect Storm: How FPGAs, Multicore CPUs, and Graphical Programming Are Changing the Economics of Embedded Design (Electronic News) 2/11/2013
FPGA Debugging Techniques to Speed Pre-Silicon Validation (EDN Magazine) 2/7/2013
Accelerated VIP Solves Firmware and Driver Integration and Validation Trade-Offs (Tech Design Forum) 1/31/2013
Extreme Code Density: Energy Savings and Methods (Chip Estimate Corp.) 1/29/2013
Developing FPGA Applications for Edition 2 of the IEC 61508 Safety Standard (EE Times Programmable Logic Designline) 1/25/2013
Discover a Better Way to Go from C-Level to Synthesis for SOC Designs (Electronic Design Magazine) 1/25/2013
Verification IP: The Questions You Should Ask (Tech Design Forum) 1/24/2013
An ESD-Efficient, Generic Low-Power Wake-Up Methodology in an SOC (Design & Reuse) 1/23/2013
Sizing up the Verification Problem (Electronic Design Magazine) 1/23/2013
Understanding SATA FIS-Based Switching (Chip Estimate Corp.) 1/22/2013
Tackling Large-Scale SOC and FPGA Prototyping Debug Challenges (EE Times EDA Designline) 1/21/2013
Get More out of System Architectures (Tech Design Forum) 1/18/2013
An Example Verification Environment for Different Types of Processor Models (Design & Reuse) 1/15/2013
Free Online Design, Simulation, Parts Search Tools (EDN Magazine) 1/14/2013
How FPGA-based Platforms Future-Proof and Enhance Adaptability of Embedded Systems (Electronic Design Magazine) 1/14/2013
The Efficient Implementation of Asynchronous Logic in COTS FPGAs (EE Times Programmable Logic Designline) 1/4/2013
Hybrid Execution and Software-Driven Verification Will Emerge in 2013 (Electronic Design Magazine) 12/19/2012
Reduce Power in Chip Designs with Sequential Clock Gating (Electronic Design Magazine) 12/17/2012
Enabling 3D-IC design (Tech Design Forum) 12/12/2012
More-than-Moore Memory Grows Up (EDN Magazine) 12/9/2012
20-nm Timing Analysis: A Practical and Scalable Approach (Tech Design Forum) 12/6/2012
Achieving Maximum Motor Efficiency Using Dual-Core ARM SOC FPGAs (EE Times Embedded) 12/1/2012
The Importance of Verifying the Architecture of an SOC Prototyping System (New Electronics Magazine) 12/1/2012
Design Reuse without Verification Reuse Is Useless (EE Times EDA Designline) 11/26/2012
ARM vs. Incumbent Microprocessor Architectures (EDN Magazine, ) 11/13/2012
EDA Vendors Roll Out Advances for 20-nm Design (DSP-FPGA) 11/13/2012
What's the Difference Between de Jure and de Facto Standards? (Electronic Design Magazine) 11/13/2012
Protecting Display Data in TrustZone-Enabled SoCs with the Evatronix Panta Family of Display Processors (Design & Reuse) 11/8/2012
Implementing Digital Processing for Automotive Radar Using SOC FPGAs (EE Times Programmable Logic Designline) 11/6/2012
SSM Policy Driven System Management Updates SoC Architecture to Meet today's Operation Complexities (Chip Estimate Corp.) 11/6/2012
Right-Sizing Your Processor Selection (EDN Magazine) 11/5/2012
RTL Analysis for Complex FPGA Designs Using a Grey Cell Methodology (EE Times Programmable Logic Designline) 10/26/2012
Small Cells: How fast and How Many? (EE Times Programmable Logic Designline) 10/22/2012
Understanding 28-nm SOC Design with ARM-Based Cores (Electronic Design Magazine) 10/19/2012
One Processor to Rule Them All? (EDN Magazine) 10/18/2012
Processor Architectures: the Sweet-Spot Spectrum (EDN Magazine) 10/18/2012
Marketing and Technology Collide in Competitive Chip Design (Electronic Design Magazine) 10/11/2012
FPGA-Based Video Surveillance Comes of Age (EE Times Programmable Logic Designline) 10/10/2012
What's the Deal with SOC Verification? (Electronic Design Magazine) 10/10/2012
M-PHY Benefits and Challenges (Chip Estimate Corp.) 10/9/2012
FPGA High-Efficiency, Low-Noise Pulse-Frequency Space-Vector Modulation-Part 1 (EDN Magazine) 10/4/2012
How Partial Dynamic Reconfiguration Helped Make an FSK Demodulator (EE Times Programmable Logic Designline) 10/2/2012
Multicore ARM SOCs Face Cache Coherency Dilemma (Chip Estimate Corp.) 10/2/2012
Removing Pessimism and Optimism in Timing Analysis (EE Times EDA Designline) 10/1/2012
Enhancing Verification through a Highly Automated Data Processing Platform (Design & Reuse) 9/26/2012
Designing a Reset-Aware OVM Testbench (EE Times EDA Designline) 9/24/2012
Interfacing QDR-II+ Synchronous SRAM with High-Speed FPGAs-Part 2 (EE Times Memory Designline) 9/17/2012
Moving to Advanced Reliability Verification (Tech Design Forum) 9/14/2012
Why IDEs for Hardware Design Fail (EE Times EDA Designline) 9/11/2012
Interfacing QDR-II+ Synchronous SRAM with High-Speed FPGAs-Part 1 (EE Times Memory Designline) 9/10/2012
How FPGAs, Multicore CPUs, and Graphical Programming Are Changing Embedded Design (EE Times Embedded) 9/5/2012
Configurable Dividers for SOC/ Block-Level Clocking (EE Times EDA Designline) 9/4/2012
Designing a NVMe-Compliant PCIe SSD (Chip Estimate Corp.) 9/4/2012
6 Reasons You Should Customize Your DSP Cores (Chip Estimate Corp.) 9/1/2012
Non-Invasive Techniques Advance Electrical Tests (EE Times Test & Measurement Designline) 8/28/2012
Growing Audio Requirements in SOCs (EE Times Audio Designline) 8/23/2012
Proposal for a Dynamically Reconfigurable Processor Architecture with Multi-Accelerator (Design & Reuse) 8/20/2012
FPGAs: An Alternative to Cloud Computing? (Electronic Design Magazine) 8/16/2012
Move to Broader Coverage in SOC Verification Metrics (Electronic Design Magazine) 8/16/2012
Understanding the Concept of X in SOC Design Flow (EDN Magazine) 8/14/2012
The Forgotten SOC Verification Team (EE Times EDA Designline) 8/13/2012
Design, Simulation and Measurement Automation: The Missing Link (Electronic Products & Technology (EP&T)) 8/10/2012
Equations and Impacts of Setup and Hold Time (EDN Magazine) 8/10/2012
Growing Audio Requirements in SOCs (EDN Magazine) 8/7/2012
The Basics of FPGA Mathematics (EE Times Programmable Logic Designline) 8/7/2012
ASIC Implementation of a Speech Detector IP-Core for Real-Time Speaker Verification (Design & Reuse) 7/24/2012
Power Awareness in RTL Design Analysis (EE Times EDA Designline) 7/23/2012
Using FPGAs to Solve Tough DSP Design Challenges (EE Times Militray & Aerospace Highlights) 7/23/2012
Design of a 8051 Microcontroller in FPGA with Reconfigurable Instruction Set (Design & Reuse) 7/19/2012
The Fundamentals of Integrating USB 3.0 IP on an SoC (Electronic Design Magazine) 7/18/2012
Implement Abstraction by Encapsulation in SystemC (Electronic Design Magazine) 7/17/2012
Understanding FPGA Processor Interconnects (Electronic Design Magazine) 7/17/2012
Embedded Success: It's About More than Just the Core (Electronic Design Magazine) 7/11/2012
Enabling Error Resilience Throughout the Embedded System (EE Times Programmable Logic Designline) 7/10/2012
Embedded Vision: FPGAs' Next Technology Opportunity (EE Times Militray & Aerospace Highlights) 7/2/2012
Prevention, Quality and Other Innovations in Hardware Debug (EE Times EDA Designline) 7/2/2012
ACE'ing the Verification of a Cache-Coherent System Using UVM (EE Times EDA Designline) 6/25/2012
Software Extends Hardware-in-the-Loop Real-Time Simulation (EE Times Automotive Designline) 6/25/2012
Optimizing FPGAs for Power: A Full-Frontal Attack (EE Times Militray & Aerospace Highlights) 6/18/2012
Sexy SoCs Are Not the Whole Story for FPGAs (Electronics Weekly) 6/18/2012
Accelerate Partial Reconfiguration with a 100% Hardware Solution (EE Times Programmable Logic Designline) 5/26/2012
AMBA 4 ACE for Heterogeneous Multiprocessing SOCs (Design & Reuse) 5/24/2012
Power: A Significant Challenge in EDA Design (EDN Magazine) 5/24/2012
FPGA Testing for DO-254 Compliance (EE Times Militray & Aerospace Highlights) 5/22/2012
Where There's a Will… There’s a Way to Better VHDL Verification (Tech Design Forum) 5/21/2012
The Growing Use of Programmable Logic in Mobile Handsets (EE Times Programmable Logic Designline) 5/17/2012
Integrating High-Level Synthesis Design into FPGA SOCs with Less Effort and Risk (DSP-FPGA) 5/15/2012
Tool Providers Focus on Improving the Efficiency of FPGA Design (DSP-FPGA) 5/15/2012
Virtual Prototyping Tools Speed Development for FPGAs with ARM-based SOC Subsystems (DSP-FPGA) 5/15/2012
Top 10 Tips for Success with Formal Analysis-Part 3 (EE Times EDA Designline) 5/14/2012
How to Use the CORDIC Algorithm in Your FPGA Design (EE Times Programmable Logic Designline) 5/12/2012
Novel Chip Technology to Power GRAPE-8 Supercomputer (HPCwire) 5/10/2012
Enough of the Sideshows: It's Time for Some Real Advancement in Functional Verification! (Electronic Engineering Times (EE Times)) 5/8/2012
Time Is Money! A Quick Fix for Those Pesky FPGA Design Errors (EE Times Programmable Logic Designline) 5/4/2012
Lessons in Developing and Deploying OVM-Compliant VIP (Design & Reuse) 5/3/2012
Verifying Today's SOCs Requires a New Approach (Electronic Engineering Journal) 5/3/2012
The Challenge of the Clock Domain Crossing Verification in DO-254 (Design & Reuse) 4/26/2012
2012 Will Be the Year of Power; Again (EE Times EDA Designline) 4/25/2012
Low Power Is Everywhere (Electronic Engineering Times (EE Times)) 4/18/2012
Automatic C-to-VHDL Testbench Generation Shortens FPGA Development Time (EE Times Programmable Logic Designline) 4/11/2012
Optimizing Performance, Power, and Area in SOC Designs Using MIPS Multi-Threaded Processors (EE Times EDA Designline) 4/4/2012
2.5D ICs Are More than a Stepping Stone to 3D ICs (EE Times Programmable Logic Designline) 3/27/2012
Virtual Platforms and RPB for Faster System Verification (Design & Reuse) 3/22/2012
Building a NAND Flash Controller with High-Level Synthesis (EE Times Memory Designline) 3/19/2012
FPGAs Unleash Potential of Flash Memory for Enterprise Applications (EE Times Programmable Logic Designline) 3/16/2012
FPGA-based Automotive ECU Design Addresses AUTOSAR and ISO 26262 Standards (EE Times Programmable Logic Designline) 3/13/2012
Software-Generated BCH As a Way to Solve Challenges of Providing Multiple Configuration IP (Design & Reuse) 3/6/2012
The Ins and Outs of Digital Filter Design and Implementation (EE Times Programmable Logic Designline) 2/29/2012
Entering the Third Epoch of EDA (EE Times EDA Designline) 2/27/2012
Application Hardware Modeling: Selective Modeling for Early Prediction of Subsystem Performances Through Simulation (Design & Reuse) 2/22/2012
How to Build a Self-Checking Testbench (EE Times Programmable Logic Designline) 2/17/2012
Bridging Software and Hardware to Accelerate SOC validation (EE Times Test & Measurement Designline) 2/15/2012
Introduction to Multisource Clock Tree Systems (Electronic Design Magazine) 2/10/2012
Refactoring Hardware Algorithms to Functional Timed SystemC Models (Design & Reuse) 2/9/2012
Programmable Logic, SOCs Simplify Power Steering, Accessory Control (EE Times Automotive Designline) 1/31/2012
Top 10 Tips for Success with Formal Analysis-Part 2 (EE Times EDA Designline) 1/30/2012
Improving SystemVerilog UVM Transaction Recording and Modeling (Design & Reuse) 1/19/2012
Design Industrial Systems on a Chip that Meet Stringent Global Safety Standards (EE Times Industrial Control Designline) 1/18/2012
Formal Techniques for Protocol Verification: A Case Study on Verifying the ARM ACE Protocol (Electronic Design Magazine) 1/11/2012
Handle Multiple Waveforms in a Software-Defined Radio Platform (EE Times RF & Microwave Designline) 1/9/2012
How Formal MDV Can Eliminate IP Integration Uncertainty (EE Times EDA Designline) 1/9/2012
The Prototype Comes of Age (EDN Magazine) 1/5/2012
FPGA or DSP Processor: Parameters to Make the Right Choice (FPGARelated.com) 12/28/2011
Automating Design Rule Waivers in SOC IP Reuse (Electronic Design Magazine) 12/27/2011
Virtual Platforms and TLMs Going Mainstream (Electronic Design Magazine) 12/27/2011
Aligning Software Development Teams through Collaborative Design Management (Electronic Design Magazine) 12/22/2011
Single-Event Effects (SEEs) in FPGAs, ASICs, and Processors-Part 2: Mitigation (EE Times Militray & Aerospace Highlights) 12/20/2011
Automated Architecture Checking of UML Based SoC Specifications (Electronic Design Magazine) 12/15/2011
Single-Event Effects (SEEs) in FPGAs, ASICs, and Processors-Part 1: Impact and Analysis (EE Times Militray & Aerospace Highlights) 12/14/2011
Combining Prototyping Solutions to Solve Hardware/ Software Integration Challenges (EE Times EDA Designline) 12/13/2011
Top 10 Tips for Success with Formal Analysis-Part 1 (EE Times EDA Designline) 12/12/2011
Display Interface and Power-Saving Challenges: The System Designer Perspective (EE Times Programmable Logic Designline) 12/6/2011
Virtual Versus Physical Prototyping: Get It Right Faster (EE Times EDA Designline) 11/28/2011
Prototyping Mesh-of-Tree NOC-Based MPSOC on Mesh-of-Tree FPGA Devices (Design & Reuse) 11/23/2011
Using FPGAs to Solve Challenges in Industrial Applications (EE Times Programmable Logic Designline) 11/22/2011
Building 3D-ICs: Tool Flow and Design Software - Part 2 (EE Times EDA Designline) 11/21/2011
How to Build a Better DC/DC Regulator Using FPGAs (EE Times Programmable Logic Designline) 11/2/2011
Overcoming 40G/100G SerDes Design And Implementation Challenges (EE Times EDA Designline) 11/2/2011
Assertion-Based Verification Benefits FPGA designs (Dataweek) 10/26/2011
Open Standards Are Better than Open Source (Electronics Weekly) 10/26/2011
Big.LITTLE Processing with ARM Cortex-A15 and Cortex-A7 (EE Times MCU Designline) 10/24/2011
Multi-FPGA NOC Based 64-Core MPSOC: A Hierarchical and Modular Design Methodology (Design & Reuse) 10/19/2011
Implementing High-Speed USB Functionality with FPGA- and ASIC-Based Designs (EE Times Programmable Logic Designline) 10/18/2011
Addressing the New Challenges of ASIC/ SOC Prototyping with FPGAs (EE Times Programmable Logic Designline) 10/12/2011
FPGA Functional Verification: Why Bother? (Electronics Weekly) 10/11/2011
Agile Hardware Development: Nonsense or Necessity? (EE Times EDA Designline) 10/10/2011
Static Formal Verification for System-Level Verification (Design & Reuse) 10/7/2011
25-28Gbps SerDes Design and Implementation Challenges (Chip Estimate Corp.) 10/4/2011
Reducing Turnaround Time with Hierarchical Timing Analysis (EE Times EDA Designline) 10/3/2011
Concurrency Checkers Can Improve Multicore Process Performance (New Electronics Magazine) 9/27/2011
Metrix-Driven Hardware/ Software System-Level Verification (Design & Reuse) 9/27/2011
A Practical Approach to IP Quality Inspection (EE Times EDA Designline) 9/26/2011
Dealing with the Pains of Technology Adoption (Electronic Design Magazine) 9/26/2011
Latches and Timing Closure: A Mixed Bag (EDN Magazine) 9/22/2011
Partial Reconfiguration in FPGA Rapid Prototyping Tools (Design & Reuse) 9/22/2011
A New Approach to Hardware Design Project Management (EE Times EDA Designline) 9/20/2011
Managing IP Quality in the SOC Era Requires a Purpose-Built DM Approach (Electronic Engineering Times (EE Times)) 9/19/2011
5 Wirebond Power Bus Watch-Outs! (Design & Reuse) 9/15/2011
Design Flow Developments Enable More-Capable Signal Processing (New Electronics Magazine) 9/13/2011
The Key to Realizing Full Multicore Design Functionality (EE Times Embedded) 9/2/2011
Breaking the Language Barriers: Using Coverage Driven Verification to Improve the Quality of IP (Design & Reuse) 9/1/2011
Many-Core: Finding the Best Multi-Processing Tile (EE Times EDA Designline) 8/29/2011
Programmable Oscillators Enhance FPGA Applications (EE Times Programmable Logic Designline) 8/29/2011
Cryptography in Software or Hardware: It Depends on the Need (EE Times Embedded) 8/28/2011
Transaction Analysis and Debug Across Language Boundaries and Between Abstraction Levels (Design & Reuse) 8/25/2011
Basics of Core-Based FPGA Design-Part 4: Implementing a Design (EE Times Embedded) 8/22/2011
Basics of Core-Based FPGA Design-Part 2: System Design Considerations (EE Times Embedded) 8/21/2011
Basics of Core-Based FPGA Design-Part 3: Picking the Right Core Options (EE Times Embedded) 8/21/2011
Developing Processor-Compatible C-Code for FPGA Hardware Acceleration (EE Times Embedded) 8/21/2011
Basics of Core-Based FPGA Design-Part 1: Core Types & Trade-Offs (EE Times Embedded) 8/17/2011
How Do I Reset My FPGA? (EE Times Programmable Logic Designline) 8/10/2011
Marrying Flexibility and Complexity Verifying a DSP in an FPGA (Electronic Engineering Journal) 8/4/2011
Performance Evaluation of Inter-Processor Communication Mechanisms on the Multicore Processors Using a Reconfigurable Device (Design & Reuse) 8/4/2011
SOC Ecosystems Become More Tightly Integrated (Chip Design Magazine) 8/1/2011
Designing with Core-Based High-density FPGAs (EE Times Embedded) 7/27/2011
Guide to VHDL for embedded software developers-Part 3: ALU Logic and FSMs (EE Times Embedded) 7/25/2011
SPVR: An IP Core for Real-Time Speaker Verification (Design & Reuse) 7/21/2011
A Guide to VHDL for Embedded Software Developers-Part 1: Essential Commands (EE Times Embedded) 7/19/2011
Guide to VHDL for embedded software developers-Part 2: More Essential Commands (EE Times Embedded) 7/19/2011
Designers Take a Fresh Look at Power Management System Design (New Electronics Magazine) 7/12/2011
How to Accelerate Genomic Sequence Alignment 4X Using Half an FPGA (EE Times Programmable Logic Designline) 7/5/2011
The Quandary of EDA Software Piracy (EDN Magazine) 7/5/2011
FPGAs 101-Part 1: Fundamental Concepts (Electronic Products Magazine) 7/1/2011
FPGAs 101-Part 2: Different Devices (Electronic Products Magazine) 7/1/2011
Debug a Microcontroller-to-FPGA Interface from the FPGA Side (EE Times MCU Designline) 6/27/2011
Breaking the Language Barriers: Using Coverage Driven Verification to Improve the Quality of IP (Design & Reuse) 6/20/2011
Down and Dirty with HW/SW Codesign-Part 1: Reviewing the Fundamentals (EE Times Embedded) 6/18/2011
Enhancing Simulation Studies with 3D Animation (EE Times EDA Designline) 6/8/2011
Improving USB 3.0 with Better I/O Management (EE Times Embedded) 6/6/2011
Software Driven Verification (Design & Reuse) 6/2/2011
Verifying Designs Before Committing to Hardware (Electronic Products Magazine) 6/1/2011
Two Methodologies for ASIC Conversion (EE Times EDA Designline) 5/31/2011
Improving Today's Multimedia Products with 3rd-Party Audio IP Solutions (EE Times Audio Designline) 5/25/2011
HW/SW Co-Verification Basics-Part 2: Software-Centric Methods (EE Times Embedded) 5/24/2011
HW/SW Co-Verification basics-Part 3: Hardware-Centric Methods (EE Times Embedded) 5/24/2011
HW/SW Co-Verification Basics-Part 4: Co-Verification Metrics (EE Times Embedded) 5/24/2011
Achieve your SOC Design Goals: Measure Twice, Cut Once! (EE Times EDA Designline) 5/23/2011
Speeding Verification of FPGA-Based Prototype Boards with the ProtoLink Probe Visualizer (EE Times Programmable Logic Designline) 5/23/2011
Overcoming the Challenges of Formal Verification and Debug (EE Times EDA Designline) 5/18/2011
Time to Exploit IDEs for Hardware Design And Verification (EE Times EDA Designline) 5/18/2011
FPGAs Try to Get Embedded (EDN Magazine) 5/12/2011
How to Build a Fast, Custom FFT from C (EE Times Programmable Logic Designline) 5/11/2011
Optimize Data Flow Video Apps By Tightly Coupling ARM-Based CPUs-to-FPGA Fabrics (EE Times Embedded) 5/10/2011
Platforms Continuum for System Realization (Embedded Computing Design) 5/5/2011
TLM 2.0 Standard into Action: Designing Efficient Processor Simulators (Design & Reuse) 5/5/2011
Developing the World'S First Real-Time 3D OCT Medical Imaging System with NI FlexRIO (EE Times Programmable Logic Designline) 4/26/2011
Plan Strategies for Adopting Model-Based Design for Embedded Applications: Part 4 - Implementation, Verification and Validation (EE Times Automotive Designline) 4/21/2011
Xilinx 7 Series FPGAs: User Guide Lite (EE Times Programmable Logic Designline) 4/19/2011
Minimal Effort Chip Design Using IP (Design & Reuse) 4/14/2011
Using Verification Coverage with Formal Analysis (EE Times EDA Designline) 4/13/2011
Implementing Different Power Features in an IP (Design & Reuse) 4/7/2011
How to Achieve Quality Assurance for Your Electronic Designs (EE Times Programmable Logic Designline) 4/4/2011
Get the Lowdown on Accellera's VIP and UVM (Chip Design Magazine) 4/1/2011
In IP We Trust? (Chip Design Magazine) 4/1/2011
System-Level Design: Five Likely 2011 Trends (Chip Design Magazine) 4/1/2011
The Missing Pieces in Power Modeling; Who's Going to Provide Them (Chip Design Magazine) 4/1/2011
Automating Design Rule Waivers in SOC IP Reuse (Design & Reuse) 3/31/2011
Complete NAND Flash Solution: Logic, PHY and File System Software (Design & Reuse) 3/31/2011
Vertically Integrated MIPI Solutions (Design & Reuse) 3/24/2011
Breaking Barriers with FPGA-Based Design-for-Prototyping (XCell Journal Online) 3/22/2011
The Real Role of EDA in the Cloud (EE Times Programmable Logic Designline) 3/22/2011
When It Comes to Runtime Chatter, Less Is Best (XCell Journal Online) 3/22/2011
What Makes an Optimal SOC Verification Strategy (EE Times EDA Designline) 3/21/2011
Complete IC Simulation Requires a Full Toolbox of Hardware and Software (EDN Magazine) 3/17/2011
Tracing Mixed-Tool Flows Graphically (EE Times EDA Designline) 3/16/2011
Treat ICs, Packages, and PCBs as System Designs (Electronic Design Magazine) 3/16/2011
Hardware/Software Integration: Closing the Gap (EE Times EDA Designline) 3/13/2011
Hardware Co-Verification Using VMM HAL-SCEMI (Design & Reuse) 3/10/2011
Introduction to SVA Assertions for Design Engineers (Design & Reuse) 3/10/2011
Planning Reset Strategy: Flow and Functionality in OVC (EE Times EDA Designline) 3/9/2011
Major Changes Expected for Physical Verification Tools as Designs Move into 28nm and Below (Electronic Engineering Times (EE Times)) 3/8/2011
How Many-Core Will Reshape EDA (EE Times MCU Designline) 3/7/2011
Which Design Comes First: Hardware or Software? (Electronic Design Magazine) 3/7/2011
CPUs in FPGAs: Many Faces to a Trend (EDN Magazine) 3/3/2011
Adding Encryption to Disk Drives Is Made Easy Using an IP Core (EE Times Programmable Logic Designline) 3/2/2011
Designing Remote Radio Heads (RRHs) on High-Performance FPGAs (EE Times Programmable Logic Designline) 2/7/2011
Compute a Histogram in an FPGA with One Clock (EDN Magazine) 2/3/2011
ESL Anyone? (EE Times EDA Designline) 2/2/2011
Achieving First-Day Multicore SOC Software Success (EE Times Embedded) 2/1/2011
How to Instrument Your Design with Simple SystemVerilog Assertions (EE Times EDA Designline) 1/26/2011
The Next Roadblock to Custom Design Productivity: Design Constraints (DAC Knowledge Center) 1/25/2011
Free I/O: Improving FPGA Clock Distribution Control (EE Times Programmable Logic Designline) 1/23/2011
Multiband Architecture for High-Speed SerDes (EE Times Embedded) 1/20/2011
Packaging Faces a "Perfect Storm" (Electronic Products Magazine) 1/19/2011
How to Implement "All-Digital" Analog-to-Digital Converters in FPGAs and ASICs (EE Times Programmable Logic Designline) 1/18/2011
Hardware-Based Floating-Point Design Flow (EE Times Embedded) 1/17/2011
How an Emerging Methodology Better Supports SOC Design (Electronic Design Magazine) 1/11/2011
Debugging for Power Consumption (New Electronics Magazine) 1/10/2011
FPGA Technology at the Pointy End of the Spear (Electronic Engineering Times (EE Times)) 1/10/2011
How Are Competitors Differentiating Cortex-M3 based MCUs? (New Electronics Magazine) 1/10/2011
When Perfect Is Good Enough (Electronic Engineering Times (EE Times)) 1/4/2011
The War Is Over: C++ and SystemC Coexist In a Single Flow (EE Times EDA Designline) 12/15/2010
Using Mixed-Signal FPGAs to Take Motion Control to the Next Step (EE Times Programmable Logic Designline) 12/10/2010
Building FPGA-Based Digital Downconverters With Graphical Design Tools (EE Times Programmable Logic Designline) 12/8/2010
ABQ: Assertion Based Qualifier Methodology for Pre-Existing Environments (Design & Reuse) 12/2/2010
Programmable ICs: The Next Innovation Engine (EE Times Programmable Logic Designline) 12/2/2010
The Evolution of Design Methodology (Electronic Engineering Times (EE Times)) 11/24/2010
The Expanding Floating-Point Performance Gap Between FPGAs and Microprocessors (HPCwire) 11/22/2010
Innovation Led Business Models for IP's In Product Engineering (Design & Reuse) 11/18/2010
Metric-Driven Validation, Verification and Test of Embedded Software (Design & Reuse) 11/10/2010
eFPGA Creator GUI Tools Suite: A Complete Hardware and Software Infrastructure for Creating Customizable eFPGA IP Blocks (Design & Reuse) 11/4/2010
Power Aware Verification of ARM-Based Designs (EE Times Embedded) 11/4/2010
Will IP Use Increase In Forthcoming SOC Design? (Electronic Engineering Times (EE Times)) 11/4/2010
Hyper Pipelining of Multicores and SOC Interconnects (EE Times EDA Designline) 11/2/2010
A Next-Gen FPGA-Based SOC Verification Platform (EE Times Programmable Logic Designline) 11/1/2010
Understanding System-Level Energy-Management Techniques and Test (EDN Magazine) 11/1/2010
Application Specific IP: Ensuring Semiconductor IP Quality (Design & Reuse) 10/28/2010
DSP Options to Accelerate Your DSP+FPGA Design (EE Times Signal Processing DesignLine) 10/25/2010
How to Reduce Board Management Costs, Failures, and Design Time (EE Times Programmable Logic Designline) 10/25/2010
What Can Be Expected from the Accellera Unified Coverage Interoperability Standard? (Electronic Design Magazine) 10/22/2010
EDA's Next Step: System-Level Design Automation (Electronic Design Magazine) 10/20/2010
How to Choose Great IP (Design & Reuse) 10/6/2010
The "Long Tail" of FPGAs (EE Times Programmable Logic Designline) 10/5/2010
Hunting that Elusive Bug (EE Times EDA Designline) 9/28/2010
What! How Big Did You Say That FPGA Is? (EE Times Programmable Logic Designline) 9/27/2010
Using the Application Modeling and Mapping Methodology for System-level Performance Analysis (EE Times Embedded) 9/26/2010
Performance Measurements of Synchronization Mechanisms on 16PE NOC-Based Multi-Core with Dedicated Synchronization and Data NOC (Design & Reuse) 9/23/2010
How to Achieve Timing Closure In Large, Complex FPGA Designs (EE Times Programmable Logic Designline) 9/21/2010
Making Biometrics the Killer App of FPGA Dynamic Partial Reconfiguration (EE Times Programmable Logic Designline) 9/21/2010
Partial Reconfiguration In FPGA Rapid Prototyping Tools (Design & Reuse) 9/17/2010
Performance Verification of a Complex Bus Arbiter Using the VMM Performance Analyzer (EE Times EDA Designline) 9/16/2010
The Basics of SerDes for Interfacing (EE Times Planet Analog) 9/16/2010
How to Achieve 1 Trillion Floating-Point Operations-per-Second In an FPGA (EE Times Programmable Logic Designline) 9/14/2010
A Primer for Successful Integration of Complex Hard IP In Physical Design (EDN Magazine) 9/13/2010
Accelerating the Development of TLM-2.0 Models Using Model Authoring Kits (MAKs) (Design & Reuse) 9/13/2010
Conquering the Memory Bottleneck (EE Times Memory Designline) 9/13/2010
Development Tool Evolution: Hardware/ Firmware (EE Times Programmable Logic Designline) 9/13/2010
Do We Need an International EDA Roadmap? (EE Times EDA Designline) 9/13/2010
Using Switched Capacitors to Create Programmable Analog Logic Blocks In Mixed-Signal Designs (EE Times Programmable Logic Designline) 8/18/2010
Comparing AMBA AHB to AXI Bus Using System Modeling (Design & Reuse) 8/16/2010
Data Storage Yields Increased Design Productivity (EDN Magazine) 8/16/2010
FPGA Compilation On-Site or In the Cloud (EE Times Programmable Logic Designline) 8/16/2010
IP Integration: Is It the Real System-Level Design? (EDN Magazine) 8/16/2010
Reduce Embedded SOC Design Cost and Optimize IP Integration (EE Times Embedded) 8/16/2010
Transaction Analysis and Debug Across Language Boundaries and Between Abstraction Levels (Design & Reuse) 8/16/2010
ESL Synthesis: Tips for Implementing a Viable ESL-Synthesis Flow (EDN Magazine) 7/30/2010
Protect Your goal with Post-Silicon Formal Verification (Design & Reuse) 7/30/2010
Customized FPGA board for ASIC Prototyping: A Novel Approach with Pre-designed Blocks and Modular FPGA (Design & Reuse) 7/29/2010
IP Re-Engineering and Design Methodology (Design & Reuse) 7/29/2010
Give the People What They Want: HLS for RTL Verification (EE Times EDA Designline) 7/21/2010
Web-Based IC Customization Revolutionizes Timing Circuits (Electronic Products Magazine) 7/1/2010
Debug Will Get Your Attention, Sooner or Later (EE Times EDA Designline) 6/29/2010
Time Is Right for Clockless Design (EE Times EDA Designline) 6/29/2010
Path-Specific Derating to Reduce Timing Pessimism (EDN Magazine) 6/25/2010
How to Make Virtual Prototyping Better than Designing with Hardware: Part 2 - The Importance of Testability In Virtual Prototyping (EE Times Embedded) 6/23/2010
How to Make Virtual Prototyping Better than Designing with Hardware: Part 1 - Use Cases for Virtual Prototyping (EE Times Embedded) 6/22/2010
Is IP Integration the Real High-Level Design? (EDN Magazine) 6/21/2010
Achieving Verification Closure with Resource and Time Constraints (EE Times EDA Designline) 6/17/2010
Altering the SOC Design Flow (EDN Magazine) 6/17/2010
Creating Virtual Platforms Using the OCP-IP Modeling Kit (Design & Reuse) 6/17/2010
Power Analysis of Clock Gating at RTL (EE Times EDA Designline) 6/17/2010
Reducing Switching Power with Intelligent Clock Gating (EE Times Programmable Logic Designline) 6/17/2010
Repeatable Results with Design Preservation (EE Times Programmable Logic Designline) 6/17/2010
A Monitor-Based Approach to Verification (TechOnLine, Inc.) 6/2/2010
Transitioning from C/C++ to SystemC in High-Level Design (EE Times Embedded) 6/1/2010
Code Coverage Convergence In Configurable IP (Design & Reuse) 5/27/2010
The "Off-the-Shelf" IPs for Today's SoCs (EE Times Embedded) 5/24/2010
Continuous Integration of Complex Reconfigurable Systems (Design & Reuse) 5/20/2010
Design Challenges in DRL (EE Times Programmable Logic Designline) 5/19/2010
Implementing PCI Express Bridging Solutions In an FPGA (Embedded Computing Design) 5/19/2010
Producing and Verifying Quality FPGA IP (Embedded Computing Design) 5/19/2010
Protecting FPGAs from Power Analysis Attacks (EE Times Programmable Logic Designline) 5/18/2010
Building Cost-Effective and Robust SOC-based Network Appliances (EE Times Embedded) 5/17/2010
The Need for Variable Precision DSP Architecture (EE Times Programmable Logic Designline) 5/15/2010
The Documentation Challenge (EE Times EDA Designline) 5/13/2010
Scratching the Surface: The 2010 EDN DSP Directory (EDN Magazine) 4/22/2010
Timing Closure On FPGAs (EE Times Programmable Logic Designline) 4/22/2010
An Application-Specific Processor for Many-Core Architectures (Design & Reuse) 4/15/2010
Incorporating Quality Into Reusable Interface IP (Design & Reuse) 4/15/2010
Treat Programmable Hardware Design As a High-Level System Task (EE Times Embedded) 4/13/2010
Soft Design and Hard Reality (Electronic Products Magazine) 4/12/2010
DDR3 Memory Interface Controller IP Speeds Data-Processing Applications (EE Times Programmable Logic Designline) 4/6/2010
Is Semiconductor Industry Consolidation Inevitable? (Electronic Engineering Times (EE Times)) 4/5/2010
Setting Up Hardware Verification Testbenches Using OVM Configuration Classes (EE Times Embedded) 4/5/2010
RTL Synthesis Can Accelerate the Entire Implementation Flow (EE Times EDA Designline) 3/31/2010
A Step-By-Step Methodical Approach for Efficient Mixed-Language IP Integration (Design & Reuse) 3/22/2010
Polyphase Techniques Let You Create Large Filters In Smaller Implementations In Mid-Range FPGAs (EDN Magazine) 3/18/2010
Building Quality Assurance Into Your Hardware: EDA Is Not Enough! (EE Times EDA Designline) 3/17/2010
The Evolution of FPGA Coprocessing (Electronic Products Magazine) 3/15/2010
Selecting an Embedded MCU: How to Avoid the Evaluation Trap? (Design & Reuse) 3/11/2010
Evolving to a Total IP Solutions to Accelerate SOC Design (Design & Reuse) 3/4/2010
The Importance of FPGA-to-ASIC Solutions to Accelerate CPU-Based Protocols (EE Times Embedded) 3/3/2010
Incorporating Quality Into Reusable IP (EE Times Embedded) 2/26/2010
Hardware Solutions to the Challenges of Multimedia IP Functional Verification (Design & Reuse) 2/25/2010
Software Architecture for IP verification in Operating System Environment (Design & Reuse) 2/25/2010
Dodging Amdahl's Law with Message Passing, FPGA-Based Parallel Processing (EE Times Programmable Logic Designline) 2/24/2010
High-Level Synthesis, Verification and Language (EE Times EDA Designline) 2/22/2010
Leveraging FPGA and CPLD Digital Logic to Implement Analog-to-Digital Converters (EE Times Embedded) 2/18/2010
Reusable VHDL IP In the Real World (Design & Reuse) 2/18/2010
Re-Configurable Platform for Design, Verification and Implementation of SOCs (Design & Reuse) 2/11/2010
Partitioning an ASIC Design Into Multiple FPGAs (EE Times Programmable Logic Designline) 2/10/2010
Improving Software Development and Verification Productivity Using IP-Based System Prototyping (Design & Reuse) 2/1/2010
Increasing Bandwidth In Industrial Applications with FPGA Co-Processors (EE Times Programmable Logic Designline) 2/1/2010
A Recipe for Verification IP: The Role of Methodology (Design & Reuse) 1/26/2010
A Nuts and Bolts Engineering Approach to Using Open Source IP (EE Times Embedded) 1/25/2010
Methodology for Rapid Development of Loosely Timed and Approximately Timed TLM Peripherals (Design & Reuse) 1/21/2010
Automating the FPGA Design Debug Process (EE Times Embedded) 1/19/2010
Using An FPGA to Tame the Power Beast In Consumer Handheld MPUs (EE Times Programmable Logic Designline) 1/13/2010
Power Supply Design Considerations for Modern FPGAs (EE Times Programmable Logic Designline) 1/6/2010
The Evolving Landscape of Digital Signal Processing (EDN Magazine) 12/3/2009
FPGA Synthesis Can Be a Leverage Point In Your Design Flow (EE Times Programmable Logic Designline) 12/2/2009
ESL Tools Take Center Stage As Designers Move Up (Electronic Design Magazine) 12/1/2009
The Best of Both Worlds: Optimizing OCP Slave Memory Behavior (EE Times EDA Designline) 11/19/2009
High-Speed Board-Layout Challenges in FPGA/SDI Sub-Systems (EE Times Programmable Logic Designline) 11/18/2009
SaaS and EDA: Are Designers Ready? (Electronic Engineering Times (EE Times)) 11/16/2009
Use Formal, Online Communication to Deliver Design Quality Closure (Electronic Engineering Times (EE Times)) 11/16/2009
Graphics Processing: When DIY Just Doesn't Make Sense (EE Times EDA Designline) 11/15/2009
Enable Low-Power Design with FPGAs (EE Times Programmable Logic Designline) 10/30/2009
Adding Hardware Acceleration to the HVL Testbench (Design & Reuse) 10/29/2009
What If the IP You Are Looking for Does Not Exist? (Design & Reuse) 10/29/2009
A Set of VHDL IPs to Evaluate Performance of Netwoks-on-Chip (Design & Reuse) 10/22/2009
Debugging FPGA Designs May Be Harder than You Expect (EDN Magazine) 10/22/2009
FPGA-Based Rapid Prototyping of ASIC, ASSP, and SoC Designs (EE Times Programmable Logic Designline) 10/21/2009
Use of an IP core Development Process to Achieve Time-to-Market and Quality Assurance in a Multi-Project Environment (Design & Reuse) 10/15/2009
FPGA Design and Verification in Mechatronic Applications (EE Times Programmable Logic Designline) 10/13/2009
IP Quality Lies Beyond Compliance Testing (EDN Magazine) 10/8/2009
Clock Sources with Integrated Power Supply Noise Rejection Simplify Power Supply Design in FPGA-Based Systems (EE Times Programmable Logic Designline) 10/6/2009
FPGA Device Reliability and the Sunspot Cycle (EE Times Embedded) 10/6/2009
Using Tcl to Create a Virtual Component in Verilog (EE Times Embedded) 10/2/2009
Don't Let Metastability Cause Problems in Your FPGA-Based Design (EE Times Programmable Logic Designline) 9/29/2009
FPGA Architectural Power-Saving Techniques at 40nm (EDN Magazine) 9/23/2009
Tool Up for the FPGA Blitz (Electronic Design Magazine) 9/22/2009
Why Programmability Is Now a Game Changer (Electronic Engineering Times (EE Times)) 9/10/2009
How FPGAs Can Address MCUs' General-Purpose I/O Scaling Wall (EE Times Programmable Logic Designline) 9/9/2009
Outsourcing an IC Design: Some Advice from the Trenches (EDN Magazine) 9/3/2009
Improving Software Driver Development and Hardware Verification Productivity using Virtual Platforms (Design & Reuse) 8/27/2009
Debugging Hardware Designs with an FPGA-Based Emulation Tool (EE Times Embedded) 8/24/2009
Fast Design Productivity for Embedded Multiprocessor through Multi-FPGA Emulation (Design & Reuse) 8/20/2009
Virtual Multi-Cores Simplify Real-Time System Design (EE Times Embedded) 7/27/2009
Programmable Chips: Piecing Together an Analog Solution (EDN Magazine) 7/23/2009
Deinterlacing with FPGAs for HDTVs (Video/Imaging DesignLine) 7/15/2009
FPGA Verification in Embedded Video-Processing Systems (EDN Magazine) 7/9/2009
High-Level Software for Embedded-System Design Doing Your Job? (EDN Magazine) 7/9/2009
Securing SoC Platform Oriented Architectures with a Hardware Root of Trust (EE Times Embedded) 7/6/2009
Debugging Hybrid FPGA Logic/Processor Designs (Electronic Products Magazine) 7/1/2009
Balancing the Power Budget (Components in Electronics (CIE)) 6/30/2009
Rapid Debug of Serial Buses in FPGAs (EE Times Embedded) 6/30/2009
Match Multicore with Multiprogramming (Electronic Design Magazine) 6/25/2009
EDA Remains the Enabler of Much-Needed Innovation (Electronic Design Magazine) 6/18/2009
Design Techniques for FPGA Power Optimization (DSP-FPGA) 6/15/2009
Power vs. Performance: The Ultimate DSP Design Challenge (DSP-FPGA) 6/15/2009
Designing Portability Into Silicon IP (EDN Magazine) 6/11/2009
Troubleshooting a Transaction-Level Model (EDN Magazine) 6/11/2009
Can MIPI and MDDI Co-Exist? (Design & Reuse) 6/8/2009
Tailored SoC Building Using Reconfigurable IP Blocks (Design & Reuse) 6/8/2009
From IP Re-use to Open Innovation - A New Trend in the Industry (Design & Reuse) 6/4/2009
H.264/AVC HDTV Motion Compensation Soft IP (Design & Reuse) 6/4/2009
Building an FPGA-Based Digital Down Converter (EE Times Embedded) 6/3/2009
Multiprocessor Debugging Challenges (DSP-FPGA) 5/15/2009
The Drive to Lower Power (DSP-FPGA) 5/15/2009
Estimating Power in FPGA Designs (EDN Magazine) 4/23/2009
Processor Architecture Not a Factor for Low-Power Mobile Systems (EE Times Signal Processing DesignLine) 4/20/2009
Protecting Software IP: What Engineers Need to Know (Electronic Engineering Times (EE Times)) 4/20/2009
Using an Interface Wrapper Module to Simplify Implementing PCIe on FPGAs (EE Times Embedded) 4/7/2009
FPGAs Reshape Embedded Design (EDN Magazine) 3/19/2009
How to Reduce Power Consumption in CPLD Designs with Power Supply Cycling (EE Times Programmable Logic Designline) 3/11/2009
How to Detect Solder Joint Faults in Operating FPGAs in Real Time (EE Times Programmable Logic Designline) 3/4/2009
Implementing DSP Functionality with FPGAs (Electronic Products Magazine) 3/1/2009
How to Control Analog Output from a CPLD Using a Pulse Width Modulator (EE Times Programmable Logic Designline) 2/24/2009
How High-Level Synthesis Can Raise the Efficiency of Design Reuse (Design & Reuse) 2/23/2009
Verifying FPGA Designs: Simulate, Emulate, or Hope for the Best? (EDN Magazine) 2/19/2009
Dynamic Instruction Set Load-In Method for a Java SOC (Design & Reuse) 2/12/2009
Migrating From SPI 4.2 To SPI 5 IP Core: Architectural Changes and Reusability (Design & Reuse) 2/9/2009
Power-Aware FPGA Design: Part 1 (EE Times Programmable Logic Designline) 2/4/2009
EDA Bashing (EE Times EDA Designline) 2/2/2009
Take the FPGA Plunge (Electronic Design Magazine) 1/29/2009
Programmable Logic Innovation Is Overdue (EE Times Programmable Logic Designline) 1/27/2009
Identifying IP cores to Protect Your Investment (Design & Reuse) 1/26/2009
Filter Banks, Part 1: Principles and Design Techniques (EE Times Signal Processing DesignLine) 1/15/2009
Using FPGAs in Reliable Automotive System Design (EE Times Automotive Designline) 1/15/2009
How to Transform Video SerDes From a Nightmare to a Dream (EE Times Programmable Logic Designline) 1/14/2009
Using Yesterday's Methodologies to Design Today'S Multi-FPGA Systems Is a Recipe for Disaster (EE Times Programmable Logic Designline) 1/7/2009
Verification IP: Solace for the Common Integration Nightmare? (New Tech Press) 12/24/2008
Planning, Adopting and Implementing Adaptive Reuse (EE Times EDA Designline) 12/16/2008
How to Exploit the Uniqueness of FPGA Silicon for Security Applications (EE Times Programmable Logic Designline) 12/10/2008
Use Algorithmic Synthesis to Solve Your FPGA Prototyping and Design Issues (Electronic Design Magazine) 12/10/2008
Verification Metrics: When is Enough Enough? (EDN Magazine) 12/5/2008
Achieve Higher Accuracy Using Mixed-Signal FPGA Calibration (EE Times Planet Analog) 12/4/2008
Reconfigurable Computing Prospects on the Rise (HPCwire) 12/3/2008
Moving Motion-Control Technology to FPGAs (EE Times Programmable Logic Designline) 12/2/2008
Video Encoding with Low-Cost FPGAs for Multi-Channel H.264 Surveillance (Video/Imaging DesignLine) 11/28/2008
Solving FPGA I/O Pin Assignment Challenges (EE Times Programmable Logic Designline) 11/19/2008
Planning, Adopting and Implementing Adaptive Reuse (EE Times EDA Designline) 11/18/2008
X Marks the Spot...the Intersection of Eco- and Financially-Friendly Computing (EE Times Programmable Logic Designline) 11/12/2008
A SystemC/TLM Based Methodology for IP Development and FPGA Prototyping (EE Times EDA Designline) 11/3/2008
Choosing the Right Processor Candidate: the 35th Annual EDN Microprocessor Directory (EDN Magazine) 10/30/2008
Re-Engineering Obsolete ICs Using FPGAs (EDN Magazine) 10/13/2008
Extending SPI4.2 Capabilities for Ethernet Services (EDN Magazine) 10/2/2008
For Checking Software without Hardware, FPGAs Are the Answer (Electronic Design Magazine) 10/2/2008
How to Defend Against The Cloning of Your FPGA Designs (EE Times Programmable Logic Designline) 9/17/2008
Building a Configurable Embedded Processor (EE Times Embedded) 9/9/2008
PCI Express Bridging Options Enable FPGA-Based Configurable Computing (EE Times Programmable Logic Designline) 9/8/2008
The Five Forces Driving the Semiconductor IP Market (Electronic Products Magazine) 9/1/2008
Dev Kits Help Alleviate Those FPGA Design Woes (Electronic Design Magazine) 8/28/2008
Microcontroller Design in FPGAs (EE Times Programmable Logic Designline) 8/20/2008
How to Interface FPGAs to Microcontrollers (EE Times Programmable Logic Designline) 7/30/2008
HDL-Design Challenges and Philosophies for Real-World ASIC Implementations (EDN Magazine) 7/24/2008
Using Programmable Logic for Efficient and Effective DSP Design (EE Times Embedded) 7/22/2008
How to Select an AES Solution (EE Times Programmable Logic Designline) 7/16/2008
Protect Your FPGA Against Piracy (Electronic Design Magazine) 7/10/2008
Where Is EDA Going Now? (EDN Magazine) 7/10/2008
How to Overcome the Increasing Management Complexity of FPGA/PCB Pin Synchronization (EE Times Programmable Logic Designline) 7/2/2008
Achieving First-time Success at 40nm (EDN Magazine) 6/12/2008
How to Raise the RTL Abstraction Level and Design Conciseness with SystemVerilog: Part 1 (EE Times Programmable Logic Designline) 4/30/2008
Reconfigurable Computing: Custom Supercomputers on Demand? (EE Times Programmable Logic Designline) 4/15/2008
Optimizing Embedded Designs (Electronic Products Magazine) 4/14/2008
Specifying Transceivers for Serial Protocols (Electronic Products Magazine) 4/14/2008
Reducing Power in Embedded Systems by Adding Hardware Accelerators (EE Times Embedded) 4/9/2008
Implement a Complete ARV Controller in a Single SOC (Electronic Design Magazine) 3/27/2008
Multimode Sensor Processing Using Massively Parallel Processor Arrays (EE Times Programmable Logic Designline) 3/18/2008
Evolving Passive Optical Networks Demand FPGA Design Flexibility (EE Times Programmable Logic Designline) 3/12/2008
Using FPGAs to Avoid Microprocessor Obsolescence (EE Times Programmable Logic Designline) 3/5/2008
Analog's Answer to FPGA Opens Field to Masses (Electronic Engineering Times (EE Times)) 2/21/2008
Comparing IP Integration Approaches for FPGA Implementation (EE Times Programmable Logic Designline) 2/20/2008
FPGA-Based Prototyping: "Productivity to Burn" (EE Times Programmable Logic Designline) 1/30/2008
Using FPGAs for HDTV Design (EDN Magazine) 1/17/2008
USB Host IP-Core Hardware and Software Concurrent Development (Design & Reuse) 1/10/2008
OCP VIP: A Cost-Effective and Robust Qualification Process for Multimedia and Telecom SOC Designs (EE Times Embedded) 1/9/2008
The Art of FPGA Construction (EE Times Embedded) 1/6/2008
Dealing with the Challenges of Integrating Hardware and Software Verification (EE Times Embedded) 1/4/2008
Wavelet Data Hiding Using Achterbahn-128 on FPGAs (EE Times Programmable Logic Designline) 12/26/2007
Quantify FPGA System-Level Simultaneous Switching Noise in a Chip/ Package/ PCB Design (EE Times Embedded) 12/21/2007
Lower the Cost of Intelligent Power Control with FPGAs (EE Times Embedded) 12/15/2007
Using Off-the-Shelf Technology with an FPGA to Replace Custom Hardware: Picking platforms, Tools (EE Times Industrial Control Designline) 12/14/2007
Applying FPGAs in System-Critical Automotive Electronics (EE Times Automotive Designline) 12/12/2007
Designing DDR3 SDRAM Controllers with Today's FPGAs (EE Times Programmable Logic Designline) 12/12/2007
Choosing the Right Industrial Control and Acquisition Hardware: FPGAs vs. PLCs vs. Custom Hardware (EE Times Industrial Control Designline) 12/7/2007
Convert an FPGA to a Gate Array at Project Start (Electronic Engineering Times (EE Times)) 12/7/2007
Ethernet and Multimedia Applications: Part 2 (EE Times Programmable Logic Designline) 11/28/2007
Ethernet and Multimedia Applications: Part 1 (EE Times Programmable Logic Designline) 11/21/2007
A –48V Hot-Swap Controller Design Targets High-Power Blades (EDN Magazine) 11/19/2007
Interfacing FPGAs to DDR3 SDRAM memories (EDN Magazine) 11/8/2007
High Noon for FPGAs: Low-cost vs. high-end Showdown (EDN Magazine) 11/5/2007
FPGA-Based Hardware Acceleration of C/C++ Based Applications: Part 4 (EE Times Programmable Logic Designline) 10/24/2007
FPGA-Based Access Flow Processors (AFPs) for DSLAM Line Cards (EE Times Programmable Logic Designline) 10/17/2007
Low-Power Portable Product Design with FPGAs (EE Times Programmable Logic Designline) 10/10/2007
FPGA-Prototyping and ASIC-Conversion Considerations (EDN Magazine) 10/3/2007
How to Implement Double-Precision Floating-Point on FPGAs (EE Times Programmable Logic Designline) 10/3/2007
Using FPGAs for Advanced Collision Avoidance Systems (EE Times Embedded) 10/3/2007
Cost-Effective Two-Dimensional Rank-Order Filters on FPGAs (EE Times Signal Processing DesignLine) 9/20/2007
Multimedia Signal Processing with Programmable Logic (Video/Imaging DesignLine) 9/14/2007
How to Enhance Signal Integrity in High-Density FPGA-based Designs (EE Times Embedded) 9/13/2007
How to Use FPGAs for Quadrature Encoder-based Motor Control Applications (EE Times Programmable Logic Designline) 9/11/2007
Top-down DSP Design for FPGAs (EE Times Programmable Logic Designline) 9/5/2007
Regression Test for OCP SystemC Channel Models (EE Times EDA Designline) 9/4/2007
FPGA-based Design Yields Low-Cost Arbitrary-Frequency Generator (EDN Magazine) 9/3/2007
How to Support Multiple SD Devices Using CPLDs (EE Times Programmable Logic Designline) 8/22/2007
Embedded Developers Should Embrace FPGAs (EE Times EDA Designline) 8/9/2007
FPGA-based Hardware Acceleration of C/C++ Based Applications: Part 2 (EE Times Programmable Logic Designline) 8/1/2007
Using Memory Analysis to Create Leaner, Faster, More Reliable Embedded Systems (DSP-FPGA.com) 8/1/2007
FPGA vs. DSP Design Reliability and Maintenance (DSP-FPGA.com) 7/25/2007
FPGA-Based Hardware Acceleration of C/C++ Based Applications: Part 1 (EE Times Programmable Logic Designline) 7/25/2007
Is FPGA a Simpler Puzzle for ASIC Designers? (EDN Magazine) 7/19/2007
How to Implement a Compact, Cost-Effective, and Low-Power Ethernet-to-Network Processor Bridge (EE Times Programmable Logic Designline) 7/11/2007
How Customer-Specific Standard Products Ease Mobile Device Design (EE Times Programmable Logic Designline) 6/20/2007
The Incredible Journey of an 800-ps Period (EE Times Programmable Logic Designline) 6/13/2007
Using FPGAs to Interface with Digital Communication Protocols (EE Times Programmable Logic Designline) 6/6/2007
How to Simplify Hardware Prototyping with EXP Modules (EE Times Programmable Logic Designline) 5/23/2007
How to Choose an RTOS for Your FPGA and ASIC Designs (EE Times Programmable Logic Designline) 5/9/2007
How to Build Ultra-Fast Floating-Point FFTs in FPGAs (EE Times Signal Processing DesignLine) 4/30/2007
HD-Video Encoding with DSP and FPGA Partitioning (EDN Magazine) 4/26/2007
A Tutorial on Tools, Techniques, and Methodology to Improve FPGA Designer Productivity (EE Times Programmable Logic Designline) 4/25/2007
How to Test the Interconnections Between FPGAs on a High-Density FPGA-based Board (EE Times Programmable Logic Designline) 4/11/2007
Designing PC Boards with Speedy FPGAs (EE Times Embedded) 4/9/2007
Expanding Applications for Low-cost FPGAs (EE Times Programmable Logic Designline) 4/4/2007
Challenge the Assumptions on FPGAs (EE Times Signal Processing DesignLine) 4/2/2007
Migrating FPGAs to Structured ASICs in Avionics to Reduce SEU Susceptibility (DSP-FPGA.com) 4/1/2007
How to Simplify the Process of Specifying Register-Maps and Auto-Generating Code and Other Deliverables (EE Times Programmable Logic Designline) 3/28/2007
Putting FPGAs to Work in Software Radio Systems: Part 3 (EE Times RF & Microwave Designline) 3/28/2007
Putting FPGAs to Work in Software Radio Systems: Part 2 (EE Times RF & Microwave Designline) 3/21/2007
FPGA Design Issues 201 (Electronic Design Magazine) 3/15/2007
How FPGAs can tackle the challenges of network security (EE Times Programmable Logic Designline) 3/14/2007
Putting FPGAs to Work in Software Radio Systems: Part 1 (EE Times RF & Microwave Designline) 3/14/2007
Design Preservation with SmartCompile and Xilinx Design Tools (EE Times Programmable Logic Designline) 3/7/2007
A New Architecture for Development Platforms Targeted to Portable Radio Applications (DSP-FPGA.com) 2/28/2007
How to Improve Design-Level Security with Low-Cost Non-Volatile FPGAs (EE Times Programmable Logic Designline) 2/28/2007
How to Design an FPGA Architecture Tailored for Efficiency and Performance (EE Times Programmable Logic Designline) 2/12/2007
Generate FPGA Accelerators from C (EE Times Signal Processing DesignLine) 2/8/2007
Getting the Most Out of ASIC Prototyping with FPGAs (EE Times Programmable Logic Designline) 2/7/2007
Getting the Most Out of ASIC Prototyping with FPGAs (EE Times Programmable Logic Designline) 2/7/2007
Reducing FPGA Compile Time Using Parallel Compilation Methodology (EE Times EDA Designline) 2/5/2007
Designing Custom Embedded Multicore Processors (EE Times Embedded) 2/1/2007
Evaluating IP with the Four Cs: Compare, Consider, Collect, and Calculate (EDN Magazine) 2/1/2007
Programmable Accelerators: Hardware Performance with Software Flexibility (EE Times Signal Processing DesignLine) 2/1/2007
How to Design 65-nm FPGA DDR2 Memory Interfaces for Signal Integrity (EE Times Programmable Logic Designline) 1/24/2007
How to Achieve Software Load-Balance by Using a Message-Based Interconnect Protocol (EE Times Programmable Logic Designline) 1/22/2007
How to Choose the Right FPGA (EE Times Signal Processing DesignLine) 1/18/2007
How to Achieve Faster Compile Times in High-Density FPGAs (EE Times Programmable Logic Designline) 1/17/2007
How to Maximize FPGA Performance (EE Times Programmable Logic Designline) 1/15/2007
FPGA Floating Point Performance: A Pencil and Paper Evaluation (HPCwire) 1/12/2007
Video and Image Processing Design Using FPGAs (Video/Imaging DesignLine) 1/12/2007
FPGAs vs. DSPs: A Look at the Unanswered Questions (EE Times Signal Processing DesignLine) 1/11/2007
Floating-point Arithmetic on FPGAs (EE Times Signal Processing DesignLine) 12/13/2006
How to Implement High-Security in Low-Cost FPGAs (EE Times Programmable Logic Designline) 12/4/2006
How to Use CPLDs to Implement a QWERTY Keypad (EE Times Programmable Logic Designline) 11/30/2006
Focus on FPGA Programmable Platform for Industrial Systems (EE Times Industrial Control Designline) 11/29/2006
Speed Hardware Development with Model-Based Design (EE Times Signal Processing DesignLine) 11/24/2006
Low-cost Kits: The New FPGA-Designer Trend (EDN Magazine) 11/23/2006
How to Use Programmable Analog for High-Power LED Color Mixing Applications (EE Times Programmable Logic Designline) 11/15/2006
How to Get More Performance in 65-nm FPGA Designs (EE Times Programmable Logic Designline) 11/7/2006
How to Utilize Advanced FPGA Features without Getting Locked into an Architecture (EE Times Programmable Logic Designline) 10/18/2006
How to Design FPGA-based Advanced PCI Express Endpoint Solutions (EE Times Programmable Logic Designline) 10/16/2006
Designing Dual-Modulus Dividers in an FPGA (EDN Magazine) 9/28/2006
How to Use CPLDs to Manage Average Power Consumption in Portable Applications (EE Times Programmable Logic Designline) 9/26/2006
How to Reduce Power Using I/O Gating (CPLDs) versus Sleep Modes (FPGAs) (EE Times Programmable Logic Designline) 9/20/2006
Analyze DSP Designs in FPGAs with the Z-Transform (EE Times Signal Processing DesignLine) 9/18/2006
How to Get the Best Cost Savings When Implementing an FPGA-to-ASIC Conversion (EE Times Programmable Logic Designline) 9/6/2006
The "Nuts and Bolts" of Integrating PCI Express Into Your Design (EE Times Programmable Logic Designline) 8/2/2006
SIC of Figuring Out the Best ASIC Solution? (Electronic Design Magazine) 7/20/2006
Core-Aassisted Approach Accelerates Debug of FPGA DDR II Interfaces (EE Times Programmable Logic Designline) 6/21/2006
FPGAs Balance Lower Power, Smaller Nodes Drip by Drip (EDN Magazine) 6/8/2006
Implementing PCI Express Designs Using FPGAs (EE Times Programmable Logic Designline) 6/7/2006
How Hybrid Structured ASICs Provide Low-Cost Solutions for Mid-Range Applications (EE Times Programmable Logic Designline) 5/10/2006
A Low-Cost Solution for FPGA-Based PCI Express Implementation (EE Times Programmable Logic Designline) 5/3/2006
Keys to Simulation Acceleration and Emulation Success (EDN Magazine) 4/27/2006
How to lower the cost of PCI Express adoption by using FPGAs (EE Times Programmable Logic Designline) 4/26/2006
FPGA Partial Reconfiguration Mitigates Variability (eeDesign (EE Times EDA News)) 4/3/2006
FPGAs for Prototyping; ASICs for Production (EE Times Programmable Logic Designline) 3/28/2006
All About FPGAs (EE Times Programmable Logic Designline) 3/21/2006
FPGAs Poised to Play in Embedded Applications (DSP-FPGA.com) 3/17/2006
Spring "Board" To FPGA Design Success (Electronic Design Magazine) 2/16/2006
Compiling FPGA Netlists for Formal Verification (eeDesign (EE Times EDA News)) 2/6/2006
Choosing Hardware IP (EE Times Embedded) 2/1/2006
Optimizing DSP Functions in Advanced FPGA Architectures (EE Times Programmable Logic Designline) 1/25/2006
Program Flash Memory Using Parallel Flash Loaders and CPLDs (EE Times Embedded) 1/24/2006
Choose the Right Mix of Processing Technologies for Embedded-System Designs (EDN Magazine) 1/19/2006
Meeting Signal Integrity Requirements in FPGAs with High-End Memory Interfaces (EE Times Programmable Logic Designline) 1/18/2006
A Practical Approach to Reusing HDL Code in FPGA Designs (EE Times Programmable Logic Designline) 12/28/2005
How to Reduce Costs by Integrating PCI Interface Functions into CPLDs (EE Times Programmable Logic Designline) 11/30/2005
Power Considerations in Designing with 90m FPGAs (EE Times Programmable Logic Designline) 11/23/2005
Building an FPGA FIFO without Using Logic Resources (EE Times Programmable Logic Designline) 11/7/2005
Dual-Port FPGA Memory Blocks: The Ultimate System Interconnect Solution? (EE Times Programmable Logic Designline) 11/2/2005
Routing Density Analysis of ASICs, Structured ASICs, and FPGAs (EE Times Programmable Logic Designline) 10/19/2005
Best Practices for Structured-ASIC Design (Electronic Engineering Times (EE Times)) 10/17/2005
FPGA Soft Processor Design Considerations (EE Times Programmable Logic Designline) 10/12/2005
Architectural-Design Considerations for Implementing Hardware Acceleration (EDN Magazine) 9/29/2005
Making the Case for Live at Power-Up (EE Times Programmable Logic Designline) 9/21/2005
One Design Fits All (EDN Magazine) 9/15/2005
How to Save Costs Using Mature Process Technologies (EE Times Programmable Logic Designline) 9/12/2005
Low-Cost FPGAs: The ASIC Alternative (Electronic Design Magazine) 9/1/2005
Good Engineering Practices Minimize Design-Porting Effort (Chip Design Magazine) 8/1/2005
Structured ASICs Deserve Serious Attention at 90 nm (EDN Magazine) 7/7/2005
Advantages Abound for a Conversion-Free, Low-Cost Path to Volume Production (Chip Design Magazine) 6/1/2005
Navigating the Silicon Jungle: FPGA or ASIC? (Chip Design Magazine) 6/1/2005
Design FPGA-Based DSPs for Performance and Power (Chip Design Magazine) 3/1/2005
How to Create Beam-Forming Smart Antennas Using FPGAs (EE Times Embedded) 2/17/2005
Sorting Data in Two Clock Cycles (EE Times Embedded) 1/27/2005

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Magazine & Journal articles on Structured ASICs

Novel Chip Technology to Power GRAPE-8 Supercomputer (HPCwire) 5/10/2012
Integrating PCIe On-Chip (Electronic Products Magazine) 4/14/2008
How to Achieve Design Flexibility for Free Using Structured ASIC Approaches (EE Times Programmable Logic Designline) 3/26/2008
Migrating FPGAs to Structured ASICs in Avionics to Reduce SEU Susceptibility (DSP-FPGA.com) 4/1/2007
How to Get the Best Cost Savings When Implementing an FPGA-to-ASIC Conversion (EE Times Programmable Logic Designline) 9/6/2006
The "Nuts and Bolts" of Integrating PCI Express Into Your Design (EE Times Programmable Logic Designline) 8/2/2006
SIC of Figuring Out the Best ASIC Solution? (Electronic Design Magazine) 7/20/2006
Implementing PCI Express Designs Using FPGAs (EE Times Programmable Logic Designline) 6/7/2006
How Hybrid Structured ASICs Provide Low-Cost Solutions for Mid-Range Applications (EE Times Programmable Logic Designline) 5/10/2006
FPGAs for Prototyping; ASICs for Production (EE Times Programmable Logic Designline) 3/28/2006
The Economics of Structured- and Standard-Cell ASIC Designs (EDN Magazine) 3/16/2006
Choosing Hardware IP (EE Times Embedded) 2/1/2006
OCP-Based Memory Access Arbitration for a Digital Sampling Oscilloscope (EE Times Programmable Logic Designline) 12/7/2005
Routing Density Analysis of ASICs, Structured ASICs, and FPGAs (EE Times Programmable Logic Designline) 10/19/2005
Best Practices for Structured-ASIC Design (Electronic Engineering Times (EE Times)) 10/17/2005
Good Engineering Practices Minimize Design-Porting Effort (Chip Design Magazine) 8/1/2005
Structured ASICs Deserve Serious Attention at 90 nm (EDN Magazine) 7/7/2005
Advantages Abound for a Conversion-Free, Low-Cost Path to Volume Production (Chip Design Magazine) 6/1/2005
Navigating the Silicon Jungle: FPGA or ASIC? (Chip Design Magazine) 6/1/2005
What Platform ASICs Are and When to Use Them (eeDesign (EE Times EDA News)) 1/10/2005
Microcontroller Design Gets Revamped (Chip Design Magazine) 1/1/2005

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Tutorials, White Papers & Application Notes on FPGAs/CPLDs/PLDs

2.5DIC, 3DIC, and 5.5DIC: Taking Integration Into the Third Dimension (Tech Design Forum)
3D Packaging and Transistor Technology Challenges and Opportunities (weSRCH)
A Complete Design Solution for Structured ASICs (Magma Design Automation, Inc.)
A Flexible Architecture to Drive Sharp Two-Way Viewing Angle and Standard LCDs (Altera Corp.)
A Guide to Understanding Optimized Processor Cores (Synopsys, Inc.)
A Guide to Using FPGAs for Application-Specific Digital Signal Processing (Xilinx, Inc.)
A Survival Guide for Selecting High-Quality IP (Synopsys, Inc.)
Accelerating WiMAX System Design with FPGAs (Altera Corp.)
Accurate Quantitative Physics-of-Failure Approach to Integrated Circuit Reliability (DfR Solutions)
Achieving Design Closure with Constraint-Driven Synthesis (Mentor Graphics Corp.)
Achieving Low Power in 65-nm Cyclone III FPGAs (Altera Corp.)
An Introduction to Home Networking (Xilinx, Inc.)
An Introduction to IEEE 1666-2011, the New SystemC Standard (Accellera)
An Introduction to the Unified Coverage Interoperability Standard (Accellera)
At 28nm, You Can't Afford a Free Lunch (Magma Design Automation, Inc.)
Benefits and Applications of the Wireless USB WHCI Host and Dual-Role Device (Synopsys, Inc.)
Best Practices for Maximizing IP Reuse in SOC, IC and FPGA Design (IC Manage, Inc.)
Block-Based Prototyping (Aptix Corp.)
Boundary Scan Tutorial (Corelis, Inc.)
Broadcast Video Infrastructure Implementation Using FPGAs (Altera Corp.)
Building a Total Quality Experience into Silicon IP: Delivering DesignWare Silicon IP into SoC Designs (Synopsys, Inc.)
Challenges with Package-on-Package (PoP) (DfR Solutions)
Clarifying Language, Methodology Confusion (Aldec, Inc.)
Combining Impulse C with uClinux for MicroBlaze-based FPGAs (Impulse Accelerated Technologies, Inc.)
Concurrent FPGA-PCB Design within an Integrated Design Environment (Aldec, Inc.)
CONNECT: Re-Examining Conventional Wisdom for Designing NoCs in the Context of FPGAs (Carnegie Mellon Electrical & Computer Engineering)
CoRAM: An In-Fabric Memory Architecture for FPGA-based Computing (Carnegie Mellon Electrical & Computer Engineering)
Corporate Standardization of FPGA Design Flow (Aldec, Inc.)
C-To-CoRAM: Compiling Perfect Loop Nests to the Portable CoRAM Abstraction (Carnegie Mellon Electrical & Computer Engineering)
Debugging SCE-MI Co-Emulation in Riviera-PRO Simulation Environment (Aldec, Inc.)
Delivering Synthesizable Verification IP for Test Benches (Bluespec, Inc.)
Design Management & IP Reuse Study (Gary Smith EDA)
Designing Flexible Fast CAMs with Virtex Family FPGAs (Xilinx, Inc.)
Designing State Machines for FPGAs (Actel Corp.)
DSP Co-Processing in FPGAs: Embedding High-Performance, Low-Cost DSP Functions (Xilinx, Inc.)
EDA Grows Again: 2011 Complete Market Trends (Gary Smith EDA)
Efficient Static Buffering to Guarantee Throughput-Optimal FPGA Implementation of Synchronous Dataflow Graphs (University of Maryland (ECE))
Embedded Instrumentation: The Future of Advanced Design Validation, Test and Debug (ASSET InterTech, Inc.)
Embedded Systems Verification (Aldec, Inc.)
Emulation: Enabling It on Every Desktop (Bluespec, Inc.)
Enabling Assertion-Based Verification (Zocalo Tech, Inc.)
Enhancing Verilog Designs with Embedded PSL (Aldec, Inc.)
Enhancing VHDL Designs with Embedded PSL (Aldec, Inc.)
Estimating FPGA Requirements for DSP Applications (Hunt Engineering, Ltd.)
Estimating Performance and Capacity of Actel Devices (Actel Corp.)
Examining ARM's Cortex Microcontroller Software Interface Standard (Feabhas, Ltd.)
Exploring Regular Fabrics to Optimize the Performance-Cost Trade-Off (eASIC Corp.)
Favorable Economics Will Drive Rapid Adoption of Certified Wireless USB (Synopsys, Inc.)
Four Reasons to Incorporate FPGA Technology Into Your Test Applications (National Instruments Corp.)
FPGA Architectures Overview (1-CORE Technologies)
FPGA Design Practices Survey (GateRocket, Inc.)
FPGA Design Tutorial (1-CORE Technologies)
FPGA Enabled Home Networking Technology Bridges: Connecting Disparate Technologies (Xilinx, Inc.)
FPGA Logic Cells Comparison (1-CORE Technologies)
FPGA Performance Benchmarking Methodology (Altera Corp.)
FPGA Synthesis: The Vendor-Independent Approach (Mentor Graphics Corp.)
FPGA vs. DSP Design Reliability and Maintenance (Altera Corp.)
FPGA-Based Design and Implementation of the 3GPP-LTE Physical Layer Using Parameterized Synchronous Dataflow Techniques (University of Maryland (ECE))
FPGAs for High-Performance DSP Applications (Altera Corp.)
FPGAs for Software Radio (Pentek, Inc.)
FPGAs Provide Reconfigurable DSP Solutions (Altera Corp.)
FPGAs Tackle DSP Applications for Communications (Pentek, Inc.)
FPGAs: Fast Track to DSP (Mentor Graphics Corp.)
FPGAs: Under the Hood (National Instruments Corp.)
Getting Started with Xilinx FPGAs Video Guide (BurchED)
Global Design Data Management Report 2012 (IC Manage, Inc.)
Global Design Management Report 2011 (IC Manage, Inc.)
Global Design Management Report 2012 (IC Manage, Inc.)
HDL Methodology Offers Fast Design Cycle and Vendor Independence (Actel Corp.)
HDL Simulation and Mathematical Modeling Integration (Aldec, Inc.)
HES Simulation Acceleration (Aldec, Inc.)
HES-7 ASIC Prototyping (Aldec, Inc.)
Hi-Fi Audio: Unveiling the Hidden dBs (Synopsys, Inc.)
High Speed FIFOs In Spartan-II FPGAs (Xilinx, Inc.)
Highest MHz Does Not Mean Highest Performance (Tensilica, Inc.)
High-Level "Plug-and-Play" Specification, Modeling and Synthesis of Pipelined Architectures with Bluespec’s PAClib (Bluespec, Inc.)
High-Performance DSP Capability within an Optimized Low-Cost FPGA Architecture (Lattice Semiconductor Corp.)
Home Networking Using "New Wires" — IEEE 1394, USB, and Fast Ethernet Technologies (Xilinx, Inc.)
How a Complete IP Solution Speeds Time-to-Market and Reduces Risk for 10-Gigabit Ethernet Applications (Synopsys, Inc.)
IC Design Management Best Practices (IC Manage, Inc.)
Implementing DSP Designs in Altera Stratix Devices (Mentor Graphics Corp.)
Implementing Multipliers with Actel FPGAs (Actel Corp.)
Implementing Three-State and Bidirectional Buses with Multiplexers in Actel FPGAs (Actel Corp.)
Improving the FPGA Design Process Through Determining and Applying Logical-to-Physical Design Mappings (BYU Configurable Computing Lab)
Information (Internet) Appliances (Xilinx, Inc.)
Integrating a PCI Express Digital IP Core into a Gigabit Ethernet Controller (Synopsys, Inc.)
Interoperable IP Delivery (Aldec, Inc.)
Introduction to Actel FPGAs (Actel Corp.)
Introduction to Boundary Scan Test and In-System Programming (Lattice Semiconductor Corp.)
Introduction to FPGA Technology: Top Five Benefits (National Instruments Corp.)
IP Reuse and Design Management in the SOC and IC Design Process (Gary Smith EDA)
IP Reuse: Design and Verification Report 2013 (IC Manage, Inc.)
Is That an Elephant in Your Flow? (Duolog Technologies)
Logical Hardware debuggers for FPGA-based Systems (BYU Configurable Computing Lab)
Low-Power USB 2.0 PHY IP for High-Volume Consumer Applications (Synopsys, Inc.)
Meeting Growing Verification Demands (Aldec, Inc.)
Methodologies for Efficient FPGA Integration into PCBs (Xilinx, Inc.)
Microprocessor Systems (Xilinx, Inc.)
Model-based DSP Implementation on FPGAs (University of Maryland (ECE))
Modeling and Implementation of DSP FPGA Solutions (Xilinx, Inc.)
Modular, Configurable Bus Architecture Targeted for Ease of IP Reuse on System-on-Chip and ASIC Devices (Portland State University, ECE Department)
Multi-Drop LVDS with Virtex-E FPGAs (Xilinx, Inc.)
Multirate Filters and Wavelets: From Theory to Implementation (Xilinx, Inc.)
On-Chip Communications Network Report (Sonics, Inc.)
Optimizing FPGAs for High-Volume Applications (Lattice Semiconductor Corp.)
Overcome Copper Limits with Optical Interfaces (Altera Corp.)
Power Considerations for USB Applications (QuickLogic Corp.)
Predicting the Power Dissipation of Actel FPGAs (Actel Corp.)
Processing Options for Implementing Vision Capabilities in Embedded Systems (Altera Corp.)
Processor Core Power Specs: A Cautionary Tale (Tensilica, Inc.)
Programmable Platform Solutions (Altera Corp.)
Prototype and Evaluation of the CoRAM Memory Architecture for FPGA-based Computing (Carnegie Mellon Electrical & Computer Engineering)
Provisioning Analog I/O in Configurable Systems (Altera Corp.)
Quantitatively Analyzing the Performance of Integrated Circuits and Their Reliability (DfR Solutions)
RapidChip and HyperTransport Technology (LSI Corp.)
RapidChip Platform ASICs vs FPGAs (LSI Corp.)
Real Time Image Rotation and Resizing, Algorithms and Implementations (Xilinx, Inc.)
Real Time Operating Systems for FPGA (Mentor Graphics Corp.)
Real-Time Stereo Vision on the PARTS Reconfigurable Computer (Rapid Prototypes, Inc.)
Reconfigurable Computing Application Frameworks (BYU Configurable Computing Lab)
Reconfigurable Processors for High-Performance, Embedded Digital Signal Processing (BYU Configurable Computing Lab)
Reconfigurable Vehicles (Xilinx, Inc.)
Reducing FPGA Costs by Saving a Speed Grade (Mentor Graphics Corp.)
Resource-Efficient Acceleration of 2-Dimensional Fast Fourier Transform Computations on FPGAs (University of Maryland (ECE))
Re-timing for Performance Improvement in FPGA Designs (Mentor Graphics Corp.)
Reverse Disaggregation: How Silicon IP Will Change the Semiconductor Supply Chain (Synopsys, Inc.)
RFC (Recursive Flow Classification) ASIC IP Core (Calsoft Labs)
Satisfying the Demand for Rapid Feature Enhancement in Consumer Display Products (Altera Corp.)
Secure Implementations of Content Protection (DRM) Schemes (Discretix Technologies, Ltd.)
Semiconductor Equipment Stocks Extended Losses Amid Fears of Deteriorating Outlook (weSRCH)
Si2 Power Aware Design Flows (Silicon Integration Initiative, Inc. (Si2))
Signal Integrity Comparisons Between Stratix II and Virtex-4 FPGAs (Altera Corp.)
Signal Processing at 250 MHz Using High-Performance FPGAs (Rapid Prototypes. Inc.)
Single Event Upsets in FPGAs (QuickLogic Corp.)
Single-chip Heterogeneous Computing: Does the Future include Custom Logic, FPGAs, and GPUs? (Carnegie Mellon Electrical & Computer Engineering)
Smart Move: A Placement-Aware Retiming and Replication Method for FPGAs (Mentor Graphics Corp.)
Soft CPU Cores for FPGA (1-CORE Technologies)
Soft Multipliers for DSP Applications (Altera Corp.)
Solving the Challenges for Terabit Networking and Beyond (Xilinx, Inc.)
Solving the Integration Challenges for USB-Enabled Designs (Synopsys, Inc.)
Straightforward IP Integration with IP-XACT RTL-TLM Switching (IPsupermarket)
Strategic Considerations for Emerging SOC FPGAs (Altera Corp.)
Stratix II DSP Performance (Altera Corp.)
Successfully Designing FPGA-Based Systems (Cadence Design Systems, Inc.)
Synchronous Dividers in Actel FPGAs (Actel Corp.)
Synthesizable FPGA Interface for Retrieving ROM Number from 1-Wire Devices (Xilinx, Inc.)
Synthesizable Models Enable Early Emulation for Complex IP (Bluespec, Inc.)
Test Vector Guidelines (Actel Corp.)
The ABC’s of 2.4 and 5 GHz Wireless LANs (Xilinx, Inc.)
The Low-Carb VHDL Tutorial (University of Central Florida, EECS)
The Need for Dynamic Phase Alignment in High-Speed FPGAs (Altera Corp.)
The Platform FPGA: Enabling The Software Radio (Xilinx, Inc.)
The SoC Interconnect Verification Challenge (Test and Verification Solutions, Ltd. (TVS))
TLM-2.0 in Action: An Example-based Approach to Transaction-Level Modeling and Model Interoperability (Open SystemC Initiative (OSCI))
Tool Assessment and Qualification with the Aldec DO-254 Compliance Tool Set (Aldec, Inc.)
Understanding the Fundamentals of PCI Express (Synopsys, Inc.)
Unifying Bug Tracking with Design-Data Management (IC Manage, Inc.)
Using Boundary Scan to Link Design and Manufacturing Test (ASSET InterTech, Inc.)
Using Cyclone III FPGAs for Clearer LCD HDTV Implementation (Altera Corp.)
Using Cyclone III FPGAs for Emerging Wireless Applications (Altera Corp.)
Using Design-Level Scan to Improve Design Observability and Controllability for Functional Verification of FPGAs (BYU Configurable Computing Lab)
Using FPGA Prototyping Board as an SoC Verification and Integration Platform (Aldec, Inc.)
Using FPGA-Based Simulation Acceleration In a Typical ASIC Design Flow (Aldec, Inc.)
Using FPGAs for Digital PLL Applications (Actel Corp.)
Using IC Manage GDP for Collaborative Custom IC (Virtuoso) and Digital SOC Design (IC Manage, Inc.)
Using Programmable Logic for Embedded Systems (Mentor Graphics Corp.)
UVM: Ready, Set, Deploy! (Accellera)
Verification and Automation Improvement Using IP-XACT (Accellera)
Verilog Tutorial (Yankee Bush Software)
VHDL PaceMaker Interactive Tutorial (Doulos, Ltd.)
VHDL Test Bench Tutorial (University of Pennsylvania, ESE)
VHDL Tutorial (Yankee Bush Software)
VHDL Tutorial (University of Pennsylvania, ESE)
Video and Image Processing Design Using FPGAs (Altera Corp.)
VirtualWires: A Technology for Massive Multi-FPGA Systems (Mentor Graphics Corp.)
Voice-Data Convergence: Voice Over IP (Xilinx, Inc.)
What Is Assertion-Based Verification? (Tech Design Forum)
What is FPGA prototyping? (Tech Design Forum)
What is SystemC? (Tech Design Forum)
What Is Transaction-Level Modeling? (Tech Design Forum)
What Is Verification IP? (Tech Design Forum)
What Is VHDL? (Tech Design Forum)
What Your SOC Designer Might Not Tell You About Power Management (Altera Corp.)
Who Defines the FPGA Interface? (Mentor Graphics Corp.)
Wireless Home Networks — DECT, Bluetooth, HomeRF, and Wireless LANs (Xilinx, Inc.)

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Tutorials, White Papers & Application Notes on Structured ASICs

A Complete Design Solution for Structured ASICs (Magma Design Automation, Inc.)
A Socket-Based µController Design (eASIC Corp.)
Achieving Design Security Requirements Using eASIC’s Technology (eASIC Corp.)
Application Specific Programmable Platform Using eASICore (eASIC Corp.)
Configurable Structured ASICs (eASIC Corp.)
Exploring Regular Fabrics to Optimize the Performance-Cost Trade-Off (eASIC Corp.)
Paradigm Shift in ASIC Technology: In - Standard Metal; Out - Standard Cell (eASIC Corp.)
RapidChip and HyperTransport Technology (LSI Corp.)
RapidChip Platform ASICs vs FPGAs (LSI Corp.)
The Platform FPGA: Enabling The Software Radio (Xilinx, Inc.)
Use of Configurable Cores in Platform-Based ASICs (eASIC Corp.)

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