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 Category: Intellectual Property: Friday, September 10, 2010
 Intellectual Property

OCP-IP Newsletter
April 2010

Enabling Rapid, Reliable Deployment of IP
into System Designs

This webcast highlights The SPIRIT Consortium's new IP-XACT 1.4 specification which expands the range of IP that can be used in an IP-XACT Design Environment and targets new applications, specifically those dealing with transactional modeling and advanced verification methodologies. IP-XACT 1.4 benefits include documentation of all aspects of IP using XML databook format, documentation of models in a quantifiable and language- independent way, and enables designers to deploy specialist knowledge in their designs.

View the webcast now.

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Suggested Tutorials, Whitepapers & Application Notes

SOCcentral news articles on Intellectual Property

Agilent Technologies' SystemVue Now Offers Modeling, Scripting Capability Using MATLAB (9/9/2010)
Ambarella A6 Chip Platform Deployed By Harmonic (9/9/2010)
CEVA's 1-GHz DSP Core Offers Performance and Power Efficiency for Next-Generation Communications and Multimedia SOCs (9/9/2010)
Samsung Introduces High Performance, Low Power Dual Cortex-A9 Application Processor for Mobile Devices (9/9/2010)
Xilinx and NSA Announce Approval of Virtex-5Q FPGA Solution for High-Grade Cryptographic Processing (9/9/2010)
GlobalFoundries Launches 28-nm ARM Cortex-A9 Processor Platform with Gate First High-K Metal Gate (9/3/2010)
Andes Technology Adopts Cadence Digital Front-End Low-Power Flow (9/1/2010)
Posedge Announces High-Performance Unified-Security (MACsec + IPSEC) Solution (9/1/2010)
Trident Microsystems Announces Plans to License Foundational MEMC Patents (9/1/2010)
Anchor Bay Introduces Intellectual Property Licensing Program (8/26/2010)
Arasan Chip Systems First to Release UHS-II PHY IP Core (8/26/2010)
Certus Semiconductor Joins IPextreme's Constellations Program (8/26/2010)
MindTree Launches Bluetooth RF IP Enabling Complete SOC Integration (8/26/2010)
Silicon Laboratories Grants Limited License for FM Radio Technology to RDA Microelectronics (8/26/2010)
Synopsys DesignWare SATA IP Enables First-Pass Silicon Success for Global Unichip Corporation (8/26/2010)
Innopower Unveils iPaaS IP Program (8/25/2010)
OCP-IP Delivers Transaction Generator Package (8/25/2010)
OCP-IP Provides Virtual Platform Leveraging Advanced OCP SystemC TLM Modeling Kit (8/25/2010)
STARC, Calypto and Virage Logic Break New Ground With Industry's Lowest Power Design Flow (8/25/2010)
Synopsys Announces Immediate Availability of DesignWare MIPI M-PHY IP in 40-nm Process Technology (8/25/2010)
TI Announces Free Windows CE 6.0 R3 Board Support Packages for OMAP-L1x and Sitara AM1x Devices (8/25/2010)
DapTechnology's 1394b FireLink Extended IP Boosts Download Performance on Ampex MiniR700 Solid State Data Recorder (8/24/2010)
HDL Design House Announces HVT M25PX VITAL Behavioral Model (8/24/2010)
Intilop Announces Acceptance of TCP/IP Off-Load Engine Silicon IP By a Major Financial Institution (8/24/2010)
KPIT Cummins Becomes Authorized Tensilica SOC Design Center (8/17/2010)
ONFI Introduces New 2.3 Specification with ECC Off-Load Functionality (8/17/2010)
Rambus and NVIDIA Sign Patent License Agreement (8/17/2010)
Aizyc Technology Announces Silicon-Proven SDIO 3.0 Host IP Core (8/16/2010)
Family of vDisplay IP Engines Enriches Pleora's Solution Set for Real-Time Networked Video Connectivity (8/16/2010)
Power.org Unveils New Power Architecture Silicon Roadmap (8/16/2010)
Synopsys Launches DesignWare USB Software Alliance Program (8/16/2010)
VarioTAP In-System Emulation Technology Supports ARM11 Core (8/16/2010)
Aplus Flash Technology Signs Agreement with IDT for 0.35-µm HiEE (8/11/2010)
Avalon's 2D FEC Enables Reduced Chip Size, Increased Power Savings (8/11/2010)
Elecard Releases Elecard Codec SDK G4 v1.3.2 with Full DirectX Video Acceleration (DXVA) Support for AVC/H.264 Format (8/11/2010)
Novatek Selects Tensilica's HiFi Audio DSP for Blu-ray Disc and DTV (8/11/2010)
SiliconReef Acquires Chipus High-Performance Analog IP Licenses (8/11/2010)
Synopsys Adds TDD Support to LTE Model Library (8/11/2010)

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Magazine & Journal articles on Intellectual Property

IP Integration: Is It the Real System-Level Design? (EDN Magazine) 8/16/2010
Reduce Embedded SOC Design Cost and Optimize IP Integration (Embedded Systems Design (embedded.com)) 8/16/2010
Customized FPGA board for ASIC Prototyping: A Novel Approach with Pre-designed Blocks and Modular FPGA (Design & Reuse) 7/29/2010
IP Re-Engineering and Design Methodology (Design & Reuse) 7/29/2010
Verifying Your Configurable OCP Interfaces (Embedded Systems Design (embedded.com)) 6/29/2010
Is IP Integration the Real High-Level Design? (EDN Magazine) 6/21/2010
Advancing Network Packet Management and Security Using Silicon Based Subsystem IP Solutions (Design & Reuse) 6/17/2010
Altering the SOC Design Flow (EDN Magazine) 6/17/2010
Creating Virtual Platforms Using the OCP-IP Modeling Kit (Design & Reuse) 6/17/2010
Power Optimization In Image Superscalar IP (Design & Reuse) 6/17/2010
Power-Grid Analysis on SOC Graphics Chip Design (EDN Magazine) 6/17/2010
Repeatable Results with Design Preservation (Programmable Logic DesignLine) 6/17/2010
The Transformation of Silicon to System Design (Electronic Products) 6/1/2010
Code Coverage Convergence In Configurable IP (Design & Reuse) 5/27/2010
Power Management for Optimal Power Design (EDN Magazine) 5/27/2010
Selecting the Right Nonvolatile Memory IP: Applications and Alternatives (Embedded Systems Design (embedded.com)) 5/24/2010
The "Off-the-Shelf" IPs for Today's SoCs (Embedded Systems Design (embedded.com)) 5/24/2010
Implementing PCI Express Bridging Solutions In an FPGA (Embedded Computing Design) 5/19/2010
Producing and Verifying Quality FPGA IP (Embedded Computing Design) 5/19/2010
Protecting FPGAs from Power Analysis Attacks (Programmable Logic DesignLine) 5/18/2010
Building Cost-Effective and Robust SOC-based Network Appliances (Embedded Systems Design (embedded.com)) 5/17/2010
A Novel Mesh Architecture for On-Chip Networks (Design & Reuse) 5/16/2010
Implementing Different Power Features In an IP (Design & Reuse) 4/29/2010
Integrating Analog Video Interface IP Into SoCs Delivers Superb Image Quality: Part 2 (EDA DesignLine) 4/29/2010
An Analysis of Blocking versus Non-Blocking Flow Control In On-Chip Networks (Design & Reuse) 4/22/2010
Choosing the Best Standard Cell Library without Falling Into the Traps of Traditional Benchmarking Methods (Design & Reuse) 4/22/2010
Scratching the Surface: The 2010 EDN DSP Directory (EDN Magazine) 4/22/2010
An Application-Specific Processor for Many-Core Architectures (Design & Reuse) 4/15/2010
Incorporating Quality Into Reusable Interface IP (Design & Reuse) 4/15/2010
Integrating Analog Video Interface IP Into SOCs Delivers Superb Image Quality: Part 1 (EDA DesignLine) 4/7/2010
A Step-By-Step Methodical Approach for Efficient Mixed-Language IP Integration (Design & Reuse) 3/22/2010
Building Quality Assurance Into Your Hardware: EDA Is Not Enough! (EDA DesignLine) 3/17/2010
Selecting an Embedded MCU: How to Avoid the Evaluation Trap? (Design & Reuse) 3/11/2010
Embedded Symmetric MultiProcessing System On a SoC with 1.6GHz PowerPC IP in 45nm (Design & Reuse) 3/4/2010
Evolving to a Total IP Solutions to Accelerate SOC Design (Design & Reuse) 3/4/2010
Incorporating Quality Into Reusable IP (Embedded Systems Design (embedded.com)) 2/26/2010
Hardware Solutions to the Challenges of Multimedia IP Functional Verification (Design & Reuse) 2/25/2010
Software Architecture for IP verification in Operating System Environment (Design & Reuse) 2/25/2010
Reusable VHDL IP In the Real World (Design & Reuse) 2/18/2010
Guidelines for Complex SOC Verification (EDA DesignLine) 2/15/2010
Re-Configurable Platform for Design, Verification and Implementation of SOCs (Design & Reuse) 2/11/2010
Tools Accurately Simulate Noise in Mixed-Signal ASICs (EDN Magazine) 2/4/2010
Improving Software Development and Verification Productivity Using IP-Based System Prototyping (Design & Reuse) 2/1/2010
Increasing Bandwidth In Industrial Applications with FPGA Co-Processors (Programmable Logic DesignLine) 2/1/2010
Waving Goodbye to Phantom DRC Errors (SCDsource) 1/27/2010
A Recipe for Verification IP: The Role of Methodology (Design & Reuse) 1/26/2010
A Nuts and Bolts Engineering Approach to Using Open Source IP (Embedded Systems Design (embedded.com)) 1/25/2010
Designing Serial ATA IP Into Your Embedded Storage Device Design (Embedded Systems Design (embedded.com)) 12/14/2009
The Evolving Landscape of Digital Signal Processing (EDN Magazine) 12/3/2009
Embedded Display Control Applications Using FPGAs (FPGA and Programmable Logic Journal) 12/1/2009
FPGA IP: Keeping Your Device Options Open (FPGA and Programmable Logic Journal) 12/1/2009
The Best of Both Worlds: Optimizing OCP Slave Memory Behavior (EDA DesignLine) 11/19/2009
Graphics Processing: When DIY Just Doesn't Make Sense (EDA DesignLine) 11/15/2009
FPGA IP: Keeping Your Device Options Open (FPGA and Programmable Logic Journal) 10/30/2009
What If the IP You Are Looking for Does Not Exist? (Design & Reuse) 10/29/2009
A Set of VHDL IPs to Evaluate Performance of Netwoks-on-Chip (Design & Reuse) 10/22/2009
Implementing an All-Digital PHY and Delay-Locked Loop for High-Speed DDR2/3 Memory Interfaces (EDN Magazine) 10/15/2009
Use of an IP core Development Process to Achieve Time-to-Market and Quality Assurance in a Multi-Project Environment (Design & Reuse) 10/15/2009
Outsourcing SoC Network Design Just Makes Sense (Electronic Design Magazine) 10/11/2009
IP Quality Lies Beyond Compliance Testing (EDN Magazine) 10/8/2009
Using Tcl to Create a Virtual Component in Verilog (Embedded Systems Design (embedded.com)) 10/2/2009
How FPGAs Can Address MCUs' General-Purpose I/O Scaling Wall (Programmable Logic DesignLine) 9/9/2009
Improving Software Driver Development and Hardware Verification Productivity using Virtual Platforms (Design & Reuse) 8/27/2009
Placement of Different Type Nodes In a Network-on-Chip Graph (Design & Reuse) 8/13/2009
First-Pass Success In Silicon Packaging (EDN Magazine) 8/6/2009
Techniques for Implementing High-Performance Processor Cores (EDN Magazine) 8/6/2009
Changing SoC Design Methodologies to Automate IP Integration and Reuse (EDA DesignLine) 7/27/2009
Virtual Multi-Cores Simplify Real-Time System Design (Embedded Systems Design (embedded.com)) 7/27/2009
Versatile OTP Can Replace Several Memories (Chip Estimate Corp.) 7/15/2009
Debugging Hybrid FPGA Logic/Processor Designs (Electronic Products) 7/1/2009
Should Dual-Rail Go Mainstream in Deep Nanometer Era? (Electronic Design Magazine) 6/29/2009
Little-Known Flash-Memory Features Protect Data and IP (EDN Magazine) 6/25/2009
Using IP Standards to Speed Path to Executable Specifications (SCDsource) 6/23/2009
SuperSpeed USB 3.0: Ubiquitous Interconnect for Next Generation Consumer Applications (Design & Reuse) 6/22/2009
Generic and Automatic Specman-based Verification Environment for Image Signal Processing IPs (Design & Reuse) 6/18/2009
SpiritEd: A Register Specification System integrating IP-XACT and Adobe FrameMaker (Design & Reuse) 6/18/2009
Designing Portability Into Silicon IP (EDN Magazine) 6/11/2009
Tailored SoC Building Using Reconfigurable IP Blocks (Design & Reuse) 6/8/2009
From IP Re-use to Open Innovation - A New Trend in the Industry (Design & Reuse) 6/4/2009
H.264/AVC HDTV Motion Compensation Soft IP (Design & Reuse) 6/4/2009
Software Interface Standard Gives New Framework (Electronic Products) 6/1/2009
A 0.79-mm2 29-mW Real-Time Face Detection IP Core (Design & Reuse) 5/25/2009
A Reusable Level 2 Cache Architecture (Design & Reuse) 5/25/2009
Processor Architecture Not a Factor for Low-Power Mobile Systems (DSP DesignLine) 4/20/2009
Protecting Software IP: What Engineers Need to Know (Electronic Engineering Times (EE Times)) 4/20/2009
Building Advanced Cortex-M3 Applications (Embedded Systems Design (embedded.com)) 4/8/2009
Debug and Testability Features for Multi-Protocol 10G SerDes (Design & Reuse) 3/9/2009
How to Control Analog Output from a CPLD Using a Pulse Width Modulator (Programmable Logic DesignLine) 2/24/2009
Trailblazing SuperSpeed USB Design and Verification (Electronic Design Magazine) 1/29/2009
Identifying IP cores to Protect Your Investment (Design & Reuse) 1/26/2009
Modern ADCs Improve CMOS Image Sensors (EDN Magazine) 1/22/2009
The Value of High-Quality IP-XACT XML (Design & Reuse) 1/19/2009
An Application Modeling and Hardware Description for Network-on-Chip Benchmarking (Embedded Systems Design (embedded.com)) 1/14/2009
Architecting the OCP uVC Verification Component (EDA DesignLine) 1/13/2009
Taking the Delay Out of Your Multicore Design'S Intra-Chip Interconnections (Embedded Systems Design (embedded.com)) 1/7/2009
IP Hardens Up Again (EDA Tech Forum) 12/31/2008
Verification IP: Solace for the Common Integration Nightmare? (New Tech Press) 12/24/2008
Planning, Adopting and Implementing Adaptive Reuse (EDA DesignLine) 12/16/2008
Planning, Adopting and Implementing Adaptive Reuse (EDA DesignLine) 11/18/2008
A SystemC/TLM Based Methodology for IP Development and FPGA Prototyping (EDA DesignLine) 11/3/2008
Choosing the Right Processor Candidate: the 35th Annual EDN Microprocessor Directory (EDN Magazine) 10/30/2008
Multicore: the Future of SOCs? (EDN Magazine) 10/30/2008
Taking the Broad View (Components in Electronics (CIE)) 10/1/2008
How to Defend Against The Cloning of Your FPGA Designs (Programmable Logic DesignLine) 9/17/2008
Building a Configurable Embedded Processor (Embedded Systems Design (embedded.com)) 9/9/2008
Comparing Low-Cost SerDes-Based FPGAs to ASSPs for PCI Express System Design (FPGA and Programmable Logic Journal) 9/9/2008
OCP-IP Spec Provides Multicore Debug Interface (SCDsource) 9/9/2008
Debunking Multicore Design Complexities (Electronic Products) 9/1/2008
The Five Forces Driving the Semiconductor IP Market (Electronic Products) 9/1/2008
On-Chip Test Capabilities Solve the Analog-Test Problem for High-speed Serial Interfaces (EDN Magazine) 8/21/2008
Build Debug and Trace Systems for Multicore SOCs (Electronic Design Magazine) 8/14/2008
Learning Not to Fear PCI Express Compliance (EDA DesignLine) 8/12/2008
I/O Ring Complexity Requires New Design Practices (SCDsource) 8/5/2008
Protect Your FPGA Against Piracy (Electronic Design Magazine) 7/10/2008
Building an FPGA Design Repository (FPGA and Programmable Logic Journal) 7/1/2008
Selecting and Integrating Mixed-Signal IP (SCDsource) 6/17/2008
RF: Will It Ever Be Plug-In IP? (EDN Magazine) 6/12/2008
Xilinx Speeds HDL Simulation with SecureIP and FAST Simulation Mode Models (FPGA and Programmable Logic Journal) 6/10/2008
FPGA Design Requires Low-Power Techniques (SCDsource) 5/6/2008
New Standards Effort Targets Verification IP Interoperability (SCDsource) 4/28/2008
Serial ATA and the Evolution in Data Storage Technology (EDA DesignLine) 4/28/2008
Integrating PCIe On-Chip (Electronic Products) 4/14/2008
Specifying Transceivers for Serial Protocols (Electronic Products) 4/14/2008
Interfacing High-Performance 32-bit Cores to MCU-based Memory Architectures (Embedded Systems Design (embedded.com)) 4/10/2008
Reducing Power in Embedded Systems by Adding Hardware Accelerators (Embedded Systems Design (embedded.com)) 4/9/2008
Implement a Complete ARV Controller in a Single SOC (Electronic Design Magazine) 3/27/2008
Using FPGAs to Avoid Microprocessor Obsolescence (Programmable Logic DesignLine) 3/5/2008
Low-Power Design for Analog/Mixed-Signal IP (EDA DesignLine) 3/4/2008
Comparing IP Integration Approaches for FPGA Implementation (Programmable Logic DesignLine) 2/20/2008
Multi-language Functional Verification Coverage for Multi-site Projects (EDA DesignLine) 2/18/2008
How to Select a DDR Memory Controller (SCDsource) 2/13/2008
Automated Formal Verification of OCP-Based IP Cores (EDA DesignLine) 1/21/2008
A Chip IP Integrator for System Level Design (Design & Reuse) 1/14/2008
USB Host IP-Core Hardware and Software Concurrent Development (Design & Reuse) 1/10/2008
OCP VIP: A Cost-Effective and Robust Qualification Process for Multimedia and Telecom SOC Designs (Embedded Systems Design (embedded.com)) 1/9/2008
Dealing with the Challenges of Integrating Hardware and Software Verification (Embedded Systems Design (embedded.com)) 1/4/2008
Lower the Cost of Intelligent Power Control with FPGAs (Embedded Systems Design (embedded.com)) 12/15/2007
Designing DDR3 SDRAM Controllers with Today's FPGAs (Programmable Logic DesignLine) 12/12/2007
FPGA Processors Take New Directions (SCDsource) 11/15/2007
OpenAccess Expands to New Horizons (SCDsource) 11/5/2007
Mixed-Signal IP Spurs Mergers, MCUs (SCDsource) 11/2/2007
4G Wireless: Evolution or Watershed in SOC Architectures? (EDN Magazine) 10/4/2007
Regression Test for OCP SystemC Channel Models (EDA DesignLine) 9/4/2007
A Bluespec Hardware Implementation of Sudoku (EDA DesignLine) 8/21/2007
Verification Methodologies Keep Pace with Complex IP (EDA DesignLine) 8/14/2007
Achieving Certified IP Quality Efficiently (EDA DesignLine) 5/29/2007
Verifying Configurable Verification Interfaces Using OCP (EDA DesignLine) 5/10/2007
Analog and Mixed-Signal Connectivity IP at 65nm and Below (EDA DesignLine) 5/7/2007
Video Codecs in SOCs Using OCP-Based Programmable Accelerator Design (Video/Imaging DesignLine) 4/27/2007
Rigorous Automated Verification Yields High Quality Silicon (EDA DesignLine) 4/24/2007
The Growing Need for Secure Storage in Automotive Systems (EDA DesignLine) 4/6/2007
Choosing to Use an SIP Rather than an SOC (EDN Magazine) 3/15/2007
FPGA Design Issues 201 (Electronic Design Magazine) 3/15/2007
Achieving Completeness in IP Functional Verification (EDA DesignLine) 2/12/2007
Evaluating IP with the Four Cs: Compare, Consider, Collect, and Calculate (EDN Magazine) 2/1/2007
A Logical Approach to NVM Integration in SOC Design (EDN Magazine) 1/18/2007
Utilizing OCP to Design a High Performance Interconnect (EDA DesignLine) 1/18/2007
Good Or No Good? An Insider Look at What Works for ESL (Electronic Design Magazine) 12/15/2006
Embedded Memory Evolves (EDN Magazine) 12/1/2006
Proprietary Architectures Defend Automotive Space (EDN Magazine) 12/1/2006
IP Plays Cautiously in Emerging Markets (EDN Magazine) 11/9/2006
How to Increase Confidence that Third-Party IP is Functionally Correct (EDA DesignLine) 10/1/2006
Verification IP Takes a Broader Role (eeDesign (EE Times EDA News)) 8/7/2006
EDN 2006 Microprocessor Directory (EDN Magazine) 8/3/2006
How to Implement an Open IP Encryption Flow (Programmable Logic DesignLine) 6/23/2006
OCP "Tags" Support High-Performance SoCs (eeDesign (EE Times EDA News)) 5/8/2006
A Hierarchy of Needs for SoC IP Reuse (eeDesign (EE Times EDA News)) 4/17/2006
IP Integration Is Standard Fare (Electronic Design Magazine) 4/13/2006
Choosing Hardware IP (Embedded Systems Design (embedded.com)) 2/1/2006
Chip Assembly Challenges and Solutions (eeDesign (EE Times EDA News)) 1/23/2006
A Practical Approach to Reusing HDL Code in FPGA Designs (Programmable Logic DesignLine) 12/28/2005
Picking the Right RTOS for a Hybrid RISC/DSP Core (Embedded Systems Design (embedded.com)) 12/26/2005
OCP-Based Memory Access Arbitration for a Digital Sampling Oscilloscope (Programmable Logic DesignLine) 12/7/2005
FPGA Soft Processor Design Considerations (Programmable Logic DesignLine) 10/12/2005
Easing Verification Challenges for IP Reuse (eeDesign (EE Times EDA News)) 8/22/2005
Algorithmic C Synthesis Fuels Functional Reuse (FPGA and Programmable Logic Journal) 8/9/2005
Aggregation Drives Successful IP Reuse (Chip Design Magazine) 8/1/2005
An IP Storm? (EDN Magazine) 6/23/2005
IP Reuse Gets a Reality Check (Chip Design Magazine) 6/1/2005
Core Sample: IP for Increased Productivity (FPGA and Programmable Logic Journal) 5/31/2005
On-Chip Nonvolatile Memory Proves Ideal for Consumer Applications (Chip Design Magazine) 5/1/2005
SPIRIT: Structure for Packaging, Integrating, and Re-Using IP within Tool Flows (Chip Design Magazine) 5/1/2005
Get the Lowdown On IP for Your Startup (Electronic Design Magazine) 4/14/2005
Outpace Your Competitors With a Solid IP Plan (Electronic Design Magazine) 4/14/2005
FPGA-based System-on-Module Approach Cuts Time to Market, Avoids Obsolescence (FPGA and Programmable Logic Journal) 2/8/2005
IP Reuse Requires a Verification Strategy (eeDesign (EE Times EDA News)) 2/8/2005
Third-Party IP: A Shaky Foundation for SOC Design (EDN Magazine) 2/3/2005
How Memory Architectures Affect System Performance (eeDesign (EE Times EDA News)) 1/31/2005

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Tutorials, Whitepapers & Conference Papers on Intellectual Property

10 Tips for Successful SOC Design (Tensilica, Inc.)
A Methodology for Performance Analysis of Network-on-Chip Architectures for Video SoC (OCP International Partnership (OCP-IP))
A Processor and DSP IP Selection Checklist (Tensilica, Inc.)
A Survival Guide for Selecting High-Quality IP (Synopsys, Inc.)
Accelerating Functional Closure: Synopsys Verification Solutions (Synopsys, Inc.)
Advanced Stimulus Generation with DesignWare Verification IP and Verification Methodology Manual for SystemVerilog (Synopsys, Inc.)
Advanced Techniques for Building Robust Testbenches with DesignWare Verification IP and Verification Methodology Manual (VMM) for SystemVerilog (Synopsys, Inc.)
Advanced Virtual Platform Validation Methodology (JEDA Technologies, Inc.)
An Initiative Towards Open Network-on-Chip Benchmarks (OCP International Partnership (OCP-IP))
An OCP TLM for Architectural Modeling (OCP International Partnership (OCP-IP))
Application Specific Programmable Platform Using eASICore (eASIC Corp.)
Benefits and Applications of the Wireless USB WHCI Host and Dual-Role Device (Synopsys, Inc.)
Beyond DDR2 400: Physical Implementation Challenges in Your SoC Design (Synopsys, Inc.)
Boost ASIC and SOC Performance by Matching Processor to Task through Automated Processor Generation (Tensilica, Inc.)
Building a Total Quality Experience into Silicon IP: Delivering DesignWare Silicon IP into SoC Designs (Synopsys, Inc.)
CAD-Based Security, Cryptography, and Digital Rights Management (15.4) (Design Automation Conference (DAC))
Coding Guidelines for Datapath Synthesis (Synopsys, Inc.)
Combining Impulse C with uClinux for MicroBlaze-based FPGAs (Impulse Accelerated Technologies, Inc.)
DDR SDRAM: A Low Cost, Yet Increasingly Complex Off-Chip Memory Solution for SoCs (Synopsys, Inc.)
Delivering Synthesizable Verification IP for Test Benches (Bluespec, Inc.)
Design in Reliability for Communication Designs (Design Automation Conference (DAC))
Designing Using the AMBA 3 AXI Protocol (Synopsys, Inc.)
DesignWare SATA AHCI Host Controller: Understanding Multi-Port Configuration and Performance (Synopsys, Inc.)
Develop or Buy Verification IP? (nSys Design Systems Pvt. Ltd.)
Embedded DDR Interfaces: Ten Tips to Success for Your SoC (Synopsys, Inc.)
Embedded SRAM Options for ASICs and SOCs (Novelics, Inc.)
Enabling Rapid Adoption of the AMBA 3 AXI Protocol-based Design with Synopsys DesignWare IP (Synopsys, Inc.)
Everything You Wanted to Know About SOC Memory (Tensilica, Inc.)
Examining ARM's Cortex Microcontroller Software Interface Standard (Feabhas, Ltd.)
Favorable Economics Will Drive Rapid Adoption of Certified Wireless USB (Synopsys, Inc.)
Five Vital Steps to a Robust Testbench with DesignWare Verification IP and Verification Methodology Manual (VMM) for SystemVerilog (Synopsys, Inc.)
Flexible Architectures for Engineering Successful MPSoCs (Design Automation Conference (DAC))
FPGAs for Software Radio (Pentek, Inc.)
Heterogeneous MP-SoC: The Solution to Energy-Efficient Signal Processing (CoWare, Inc.)
Heterogeneous MPSoC: The Solution to Energy-Efficient Signal Processing (Design Automation Conference (DAC))
Hi-Fi Audio: Unveiling the Hidden dBs (Synopsys, Inc.)
High Performance Connectivity IP: Avoiding Pitfalls when Selecting an IP Vendor (Synopsys, Inc.)
Highest MHz Does Not Mean Highest Performance (Tensilica, Inc.)
How a Complete IP Solution Speeds Time-to-Market and Reduces Risk for 10-Gigabit Ethernet Applications (Synopsys, Inc.)
How System-Level Trade-Offs Drive Data Converter Decisions (Synopsys, Inc.)
How to Avoid the Traps and Pitfalls of SOC Design (Tensilica, Inc.)
How to Increase ASICs and SOC Computational Performance with Long-Word Processors (Tensilica, Inc.)
Implementing Floating-Point IP for the Right Accuracy and Quality of Results (QoR) (Synopsys, Inc.)
Implementing Physical Layer Connectivity IP in Deep Sub-Micron Technologies (Synopsys, Inc.)
Integrating a PCI Express Digital IP Core into a Gigabit Ethernet Controller (Synopsys, Inc.)
Intellectual Property Business Models (Mentor Graphics Corp.)
IP Exchange: I'll Show You Mine if You'll Show Me Yours (53.1) (Design Automation Conference (DAC))
IP Reuse Creation for System-on-a-Chip Design (Mentor Graphics Corp.)
IP Solutions for Synchronizing Signals that Cross Clock Domains (Synopsys, Inc.)
Licensable Processors: More Than Just Design IP (StarCore)
Life Begins at 65 – Unless You Are Mixed-Signal? (Synopsys, Inc.)
Low-Power USB 2.0 PHY IP for High-Volume Consumer Applications (Synopsys, Inc.)
Maintaining Consistency Between SystemC and RTL System Designs (Design Automation Conference (DAC))
Meeting Timing Budgets for DDR Memory Interfaces (Synopsys, Inc.)
Modeling OCP Interfaces in SystemC: Standards built on top of OSCI’s TLM-2 (OCP International Partnership (OCP-IP))
On-line Detection of Control-Flow Errors in SoCs By Means of an Infrastructure IP Core (Politecnico di Torino)
PANEL: Building a Verification Test Plan: Trading Brute Force for Finesse (Design Automation Conference (DAC))
PANEL: Differentiate and Deliver: Leveraging your Partners from Product Concept to Production (CEO Panel) (Design Automation Conference (DAC))
PCI Express: A Technology-laden Technology for the Future (ASIC Architect, Inc.)
PCI Express: Driving the Future (ASIC Architect, Inc.)
PCI Express: Sizing Replay Buffer Appropriately and Achieving High Throughput (ASIC Architect, Inc.)
Phase-Change Memory Becomes a Reality (Objective Analysis)
Processor Core Power Specs: A Cautionary Tale (Tensilica, Inc.)
Processor Ports and Queues: Easily Overcome I/O-Bandwidth Obstacles in Your Next ASIC or SOC Design (Tensilica, Inc.)
Reduce Power, Area and Routing Congestion: Analysis of a High-Performance On-Chip-Bus Interconnect (Synopsys, Inc.)
Reducing AMBA-based SoC Design Time by More Than 50% Using coreAssembler (Synopsys, Inc.)
Reverse Disaggregation: How Silicon IP Will Change the Semiconductor Supply Chain (Synopsys, Inc.)
Si2 Power Aware Design Flows (Silicon Integration Initiative, Inc. (Si2))
Si2 Power Reduction Stimulus and Low Power Design Techniques (Silicon Integration Initiative, Inc. (Si2))
Socket-Centric IP Core Interface Maximizes IP Applications (OCP International Partnership (OCP-IP))
Soft CPU Cores for FPGA (1-CORE Technologies)
Solving the Integration Challenges for USB-Enabled Designs (Synopsys, Inc.)
Standard Debug Interface Socket Requirements for OCP-Compliant SoCs (OCP International Partnership (OCP-IP))
Straightforward IP Integration with IP-XACT RTL-TLM Switching (IPsupermarket)
Technology: Develop Or License? (StarCore)
The Good? The Bad? The Ugly? IP Perspectives from Vendor to SoC Integrator (Synopsys, Inc.)
The Importance of Sockets in SOC Design (OCP International Partnership (OCP-IP))
The Open Verification Methodology (OVM), (OVM World)
The System-on-Chip Integration Challenge: The Need for Design-for-Debug Tools and Technologies (DAFCA, Inc.)
The What, Why, and How of Configurable Processors (Tensilica, Inc.)
Three SOC Application Segments Require Embedded OTP Memory (Kilopass Technology, Inc.)
To Develop or Buy a Verification IP (nSys Design Systems Pvt. Ltd.)
Understanding the Fundamentals of PCI Express (Synopsys, Inc.)
Using Impulse C with BlueCat Linux 5.4.2 on MicroBlaze via FSL (Impulse Accelerated Technologies, Inc.)
Using Processors in the SOC Dataplane (Tensilica, Inc.)
Viterbi Algorithm for Decoding of Convolutional Codes (1-CORE Technologies)
Xtensa Architecture and Performance (Tensilica, Inc.)

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