October 11, 2006 -- MIPS Technologies, Inc. today unveiled a new platform strategy for its entire range of MIPS processors. The architecture will be implemented with MIPS Technologies and partner intellectual property (IP), with all platform usages fully tested and validated under the company's new MIPS-Verified program.

MIPS Technologies will leverage its extensive ecosystem, including software tool and RTOS vendors, and IP and Electronic System-Level (ESL) companies to ensure full software support for SOC-it Platforms.

The SOC-it Platform is a defined set of components for use in platform-based designs with MIPS cores. MIPS Technologies is defining the basic hardware platform as well as a Hardware Abstraction Layer (HAL), allowing the underlying hardware to be changed without affecting software compatibility.

There are two elements of the hardware platform: The first part is a hardware kernel of components, available directly from MIPS Technologies. This consists of functionality critical to maximizing system performance, including the memory sub-system, interrupts and on-chip interconnect. The second consists of the common peripherals required in most embedded systems today, including Real Time Clock (RTC), Serial port (UART) and General Purpose I/O (GPIO). Designers may choose the source of the common peripheral IP, but still retain software compatibility by use of the HAL.

The first component of the SOC-it Platform is the SOC-it L2 Cache Controller, designed to minimize memory latency, reducing system costs and power consumption. Fully synthesizable, the SOC-it L2 Cache Controller works seamlessly with all MIPS Technologies OCP-based cores and uses standard cell libraries and memory arrays. The SOC-it L2 Cache Controller is available today to early access customers.