October 24, 2006 -- ARM today announced the availability of its new emBISTRx embedded memory test and repair system that is tightly integrated with the ARM Advantage and Metro memory compilers, part of its family of Artisan physical IP. The ARM fully embedded memory sub-system with integrated built-in-self-test (BIST) and built-in-self repair (BISR) IP increases overall chip yield to reduce chip cost, raise profit margins and enhance manufacturing test quality for Advantage and Metro memories for 45nm, 65nm and 90nm.

Unlike existing approaches where different controller types are required for different types of memory, the advanced ARM emBISTRx system is based on a hierarchically distributed architecture. With the ARM solution, a centralized shared BIST/BISR controller manages many different sizes and types of register files and memories with smart wrappers designed to be placed close to the memory instance. The benefit of ARM's integrated approach is that it minimizes the area impact on the overall memory sub-system through optimal partitioning of the test and repair logic between the controller, wrapper and memory macro. Depending on the design and implementation, average area reduction in the range of 20 to 30% can be observed as compared to conventional approaches.

In addition, the ARM emBISTRx solution reduces the number of interconnects and routing congestion, which results in area savings and faster timing closure. This area efficient, architectural approach allows designers to optimize timing-critical paths and enables at-speed testing, a critical requirement for many high-speed consumer and enterprise applications.

To enhance design productivity, the ARM emBISTRx system includes an automation tool to insert and stitch the BIST/BISR logic into the design, which reduces implementation time and eliminates design errors. The ARM emBISTRx system is tightly integrated with the ARM memory compilers to offer designers an easy-to-use solution for implementing the ARM embedded memory sub-system.

In addition to the traditional approach of targeting standard memory fault types, the ARM emBISTRx system includes algorithms that detect real world silicon defects in nanometer technology such as excessive leakage, weak bits, and subtle behavior such as resistive shorts and opens that can result in low yield. The defect-based BIST algorithms are architected to minimize test escapes, which can potentially save millions of dollars in cost for high-volume products. The ARM emBISTRx system is tuned to ARM's specific memory redundancy architecture, which is based on memory defect data, bit-cell yields and related foundry recommendations.

Availability