December 10, 2007 -- OneSpin Solutions GmbH today announced its stand-alone 360 EC-FPGA equivalence checker, which the company boasts is the first sequential equivalence checking solution dedicated to and priced for the FPGA market, and the only equivalence checker to support all sequential optimizations performed by FPGA synthesis tools. It lets designers verify functionality without disabling the advanced synthesis optimizations vital to achieving functional, performance and cost goals.

Formerly an extension of OneSpin’s 360 EC-ASIC equivalence checker, 360 EC-FPGA now is packaged stand-alone and priced for broad application in the FPGA market. OneSpin also has extended 360 EC-FPGA’s support to include all Altera Stratix and Cyclone FPGAs, and HardCopy; most Xilinx Spartan and Virtex products; and the Synplicity Synplify Pro synthesis flow, including gated clock conversion.

Synthesis tool independent, 360 EC-FPGA verifies functional equivalence between the register transfer level (RTL) code and post-synthesis FPGA netlist, and between the post-synthesis netlist and post-place-and-route FPGA netlist. It efficiently proves, without time-consuming simulation, that design functionality is preserved through all implementation phases, detecting errors and mismatches introduced by sophisticated FPGA synthesis optimizations, and dramatically reducing debug time. The solution supports both prototyping and production-part verification.

Pricing and Availability