January 21, 2008 --Ponte Solutions, Inc. has announced an enhanced YA System, version 0801, offering new defect analysis capabilities and enhanced features. This new YA release can now analyze butted contacts, diffusion contact to gate shorts, source-drain shorts, and isolated contacts and vias. In addition, Ponte has enhanced the ease-of-use for its embedded memory analysis capabilities.

By applying the YA System’s "what-if" capabilities, designers can instantly compare the sensitivity of their design, and each major design block, to changes in the defect rates for different DFM mechanisms. Moreover, by providing a quantitative Yield Sensitivity Index (YSI) to different design cockpits, from layout editors to place and route suites, the YA system lets design teams quickly determine the correct layout solution to use.

The new release further enhances the value of Ponte’s YA System at the full-chip level by providing systematic failure analysis in addition to the prior random-defect-analysis capabilities. Full-chip analysis also allows trade-off scenarios between different memory redundancy schemes for all the different memory types used in an SOC, a capability unique to the YA System. When designers couple the memory analysis with the "what-if"” capability, they can optimize memory redundancy schemes considering different defect projections.

"The Pyxis NexusRoute offering allows design teams to simultaneously enhance the performance, power and yield of their SOC designs,"” said Mitch Heins, Vice President of Marketing at Pyxis Technology. "Ponte is a part of Pyxis’ yield-aware solution and we continue to be impressed by the ongoing roadmap of new features they provide."

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