March 4, 2008 -- Tela Innovations, an early-stage technology company focused on addressing the challenges of scaling semiconductor manufacturing to 45nm and beyond, today unveiled its business strategy and technology vision for using on-grid, straight-line, one-dimensional layout structures to provide a more efficient and reliable way to design and manufacture next generation chips.

The company plans to offer a design solution that uses pre-defined physical topologies, applicable for use in logic, embedded memory, analog and I/O functions. When synthesized and routed as part of the overall design, the solution enables a lithography-optimized layout. The resulting benefits for designers, equipment suppliers and manufacturers include improvements in variability, performance, leakage and area without significant impact on existing design methodologies, equipment sets or process technologies.

The Tela solution consists of regular-patterned, pre-defined topologies consisting of straight lines with no bends, jogs or shoulders. The topologies can be used to create the usual array of ASIC/SOC IP (standard cell libraries, memory compilers, I/O cells, etc.). The approach provides the designer and manufacturer with a fixed set of interactions between shapes, reducing the unpredictable variation induced by more random layout methodologies. While related to and supportive of traditional design rules that manufacturers provide – which tell a designer what not to do – Tela’s topological-based approach pro-actively guides a designer on what to do with a series of structures that produce regular, predictable circuit layouts. The resulting logic blocks have a lower k1 lithography limit.

"The notion of a comprehensive design methodology that presents a finite set of well-defined interactions to our manufacturing partners is appealing to us in terms of reducing variability, as well as improving the efficiency of the design process," said Nick Yu, Qualcomm Vice President of Engineering. "Tela’s approach looks promising in its ability to provide a structured design style while meeting our design objectives. The evaluation results we are seeing for advanced process technologies are impressive."

In early test cases, Tela’s solution has proven to reduce area, improve performance and limit leakage in designs targeting advanced processes. One customer test case resulted in a 15% area reduction and a 2.5X reduction in leakage using a 45-nm process. In addition, the cells and resulting blocks created using the Tela solution have been successfully implemented using existing production design flows and tools.

Implementing the Tela solution

Layout and timing generation using the Tela solution is a streamlined process, as the elements of the solution "snap" together, allowing complex logic structures to be quickly created. The designer need not touch circuit transistors to utilize the Tela architecture. These physical topologies can be optimized in conjunction with a manufacturer’s OPC algorithms and process technologies, resulting in smaller die area. An additional benefit of this approach is that this set of topologies can be pre-qualified as part of the process development, resulting in more rapid deployment of design enablement for new process technologies.

The Tela solution is delivered as a physical design representation (GDSII) of a customer’s design IP. Tela’s initial focus is on applying its solution to standard cell logic followed by embedded SRAM memories, analog and I/O. It is Tela’s strategy to partner with customers’ IP development teams to enable Tela’s proprietary solution to be adopted and deployed for production IC design.