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 Category: News: Latest News: Friday, September 03, 2010
Nusym Debuts with Focus on Intelligent Verification  
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May 15, 2008 -- Nusym Technology, Inc. formally introduced itself as a verification solutions provider targeting one of the most critical problems in electronic design: developing confidence in the design in a fraction of the time and resources of current methods. Nusym is focused on an "intelligent verification" approach that leverages design insight to automatically drive rapid verification closure.

The company has raised $8 million of capital to date. Nusym's investment funding comes from premiere firms such as Woodside Funds, Draper Richards, L.P., as well as prominent EDA veterans, including Lucio Lanza and John Sanguinetti.

"With current verification methods, it is possible to get 70 to 80% coverage but it takes an enormous investment of time and resources to improve beyond that," stated Venktesh Shukla, President and CEO of Nusym. "This problem has been well understood for over a decade but attempts to solve it thus far have fallen short. This is where Nusym is focused, on how to improve coverage automatically."

Nusym's technology is currently being evaluated on a number of leading edge designs at its semiconductor partners. Nusym will announce its flagship product at a later date.

"We find Nusym to have a very promising verification technology. It can run on very large design blocks and target hard to hit coverage points," said Dan Smith, Director of CAD for NVIDIA.

Importance of intelligent verification

Today there is no way to ascertain whether a design has been fully verified with 100% confidence, elevating the risk of undiscovered faults, or bugs, in the final product. To date, formal and semi-formal approaches applied a more "intelligent" verification style, leveraging design internals to improve effectiveness. However, their use on full designs has been impractical due to severe capacity limitations and their inability to leverage current testbench infrastructure.

An ideal, "Intelligent Verification" approach would be able to use existing testbenches, along with the design, and automatically determine how to maximize coverage. At the same time it would be able to direct the user to reasons why certain coverage points were not being detected. Such an approach would avoid the unnecessary random wandering of constrained random test methods to find a bug; instead it would automatically track efficient traces through the design to coverage points. Requiring "white box" analysis of the design and testbench, intelligent verification would also ensure that no simulation cycles are wasted in verifying items that have already been tested.

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Keywords: Nusym Technology, verification, ASIC design, EDA tools,
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