July 14, 2008 -- Calypto Design Systems has unveiled a new version of its SLEC System-HLS (high-level synthesis) product that is fully integrated with Cadence Design Systems’ new C-to-Silicon Compiler high-level synthesis technology.

Calypto and Cadence joined forces to deliver a dynamic, system-level design solution that increases designer productivity by automating the C-to-Silicon Compiler and SLEC (Sequential Logic Equivalence Checker) verification flow. SLEC System-HLS, based on Calypto’s patented sequential analysis technology, verifies that the register transfer level (RTL) code generated by C-to-Silicon Compiler is functionally equivalent to the original SystemC code.

"The industry requires formal equivalence checking in high-level synthesis flows," states Hisaharu Miwa, General Manager of Design Technology Division, LSI Product Technology Unit, Renesas Technology Corp., whose design team was an early adopter of the integrated Cadence/ Calypto flow. "We found that the Calypto SLEC System-HLS and Cadence C-to-Silicon Compiler integration provides us an excellent system-level formal verification flow, saving our design team significant time and maximizing productivity."

SLEC a functional verification solution to formally verify equivalence between electronic system level (ESL) models and RTL implementations. SLEC System-HLS comprehensively verifies the output of C-to-Silicon Compiler, eliminating the need for many time-consuming simulation regressions.

"Calypto’s SLEC System-HLS product has become the standard for system-level equivalence checking," said Michael McNamara, VP/GM of the Cadence C-to-Silicon Compiler technology incubator. "Adding a tight integration between SLEC System-HLS and C-to-Silicon Compiler to our design and verification flows built around both the Encounter digital IC design and Incisive verification platforms enables Cadence to provide a comprehensive solution for system level design and verification."

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