December 14, 2011 -- Synopsys, Inc. and Global Unichip Corp. (GUC) today announced that GUC has achieved more than 1GHz on a dual-core ARM Cortex-A9 MPCore processor with Synopsys IC Compiler, a key component of Synopsys' Galaxy Implementation Platform. Synopsys' high-performance Galaxy implementation methodology was instrumental in achieving more than 1GHz frequency with minimum power, while reducing schedule risk.

"We faced several challenges to meet the frequency target for our high-end processor core-based designs, which motivated us to adopt IC Compiler," said Albert Li , Director, Design Development, Design Service Division, GUC. "Along with Design Compiler Topographical, IC Compiler's design-closure capabilities were critical in closing the frequency gap and helping us tape-out on time. We have standardized this flow for our 40- and 28- nanometer core hardening needs."

The five-million-gate, dual-core ARM Cortex-A9 processor, intended for high-end digital television chips, was fabricated on a TSMC 40-nm low-power process. It achieved a sign-off frequency of 1GHz at the worst process corner and 1.3GHz at the typical process corner, without requiring the use of overdrive voltage. GUC used the Synopsys Galaxy implementation methodology to overcome the design challenges associated with achieving this level of operating frequency and power, including:

Sensitivity of high-performance designs to memory macro placement, making it difficult to meet timing between the memories and processors. Placement of register banks for improved frequency and routability, often requiring support for structured placement techniques. High utilization in excess of 80%, requiring timing and congestion to be managed from the outset, starting with synthesis through place-and-route. Tight skew and latency requirements for clock distribution networks.