Page loading . . .

  
 Category: News: Latest News: Sunday, May 19, 2013
New Reference Designs Enhance Embedded Function Block of Lattice MachXO2 PLD Family  
 Printer friendly
 E-Mail Item URL

June 4, 2012 -- Lattice Semiconductor Corp.has announced the immediate availability of four new reference designs for the low cost, low power MachXO2 family of programmable logic devices (PLDs). The new reference designs simplify and enhance the usability of the built-in I2C, SPI and user Flash memory functions in the MachXO2 device's Embedded Function Block (EFB). Five new demonstration designs and three updated application notes focused on the embedded, Flash memory-based EFB are also now available.

Since the MachXO2 family's production release, hundreds of organizations have utilized the EFB's built-in I2C, SPI and Flash memory functions to interface with microprocessors, microcontrollers, memories and other system peripherals in applications such as I/O expansion and bridging, data storage, configuration and power sequencing. Now, the new reference designs extend EFB ease-of-use with ready-to-use RTL code for the following functions, each with standard data and command interfaces:

  • I2C-Slave (Lattice reference design number RD1124)
  • SPI-Slave (RD1125)
  • UFM access (RD1126)
  • Embedded programming (RD1129)

The RTL code is fully commented and parameterized, so it can be easily edited for customized implementations.

The five new demonstration designs implement the EFB reference designs on Lattice low cost hardware development kits, including the discounted MachXO2 Pico Development Kit, in the following system configurations:

  • I2C Master with I2C Slave (Lattice demonstration design number UG55)
  • SPI Master with SPI Slave (UG56)
  • Master I2C and SPI Using C and the LatticeMico8 Microcontroller (UG54)
  • Programming via the Wishbone bus interface (UG57)
  • Embedded programming via I2C (UG58)

These designs, each with commented, pre-verified RTL and C code, are easily re-usable to help engineers get a head start on their own implementations.

Pricing and Availability

Lattice's entire portfolio of reference designs optimized for the MachXO2 family can be downloaded at no cost from the Lattice website at www.latticesemi.com/ip.

Promotional pricing for the MachXO2 Pico Development Kit is $29 for kits ordered via the Lattice online store and through Lattice distributors through December 31, 2012, or while promotional quantities last.

All MachXO2 PLDs are fully production qualified and have been shipping since 2011.



Go to the Lattice Semiconductor Corp. website to find additional information.

E-mail Lattice Semiconductor Corp. for more information.

Read more about
Lattice Semiconductor Corp.
on SOCcentral.com


Keywords: FPGAs, field programmable gate arrays, FPGA design, PLDs, CPLDs, complex programmable logic devices, Lattice Semiconductor MachXO2, reference designs,
601/38632 6/4/2012 277 37


Designer's Mall
0.890625



 Search for:
            Site       Current Category  
   Search Options

Subscribe to SOCcentral's
SOC Explorer
Newsletter
and receive news, article, whitepaper, and product updates bi-weekly.

Exec Viewpoint

Maximizing the Value of Your Internal IP


Warren Savage
CEO, IPextreme

Exec Viewpoint

Yes, Virginia,
There Is a
Stitch-and-Ship


Dave Johnson
VP of Sales
Breker Verification

Odd Parity

Lets' Go On
with the Show!


Mike Donlin
The Write Solution

Odd Parity Archive

Barbara's Bytes

So, Just What
Is ESL


Barbara Tuck
Senior Editor,
SOCcentral

SOCcentral Job Search

SOC Design
ASIC Design
ASIC Verification
FPGA Design
CPLD Design
PCB Design
DSP Design
RTOS Development
Digital Design

Analog Design
Mixed-Signal Design
DFT
DFM
IC Packaging
VHDL
Verilog
SystemC
SystemVerilog

Special Topics/Feature Articles
3D Integrated Circuits
Analog & Mixed-Signal Design
Design for Manufacturing
Design for Test
DSP in ASICs & FPGAs
ESL Design
Floorplanning & Layout
Formal Verification/OVM/UVM/VMM
Logic & Physical Synthesis
Low-Power Design
MEMS
On-Chip Interconnect
Selecting & Integrating IP
Signal Integrity
SystemC
SystemVerilog
Timing Analysis & Closure
Transaction Level Modeling (TLM)
Verilog
VHDL
 
Design Center
Whitepapers & App Notes
Live and Archived Webcasts
Newsletters


About SOCcentral.com

Sponsorship/Advertising Information

The Home Port  EDA/EDA Tools  FPGAs/PLDs/CPLDs  Intellectual Property  Electronic System Level Design  Special Topics/Feature Articles  Vendor & Organization Directory
News  Major RSS Feeds  Articles Online  Tutorials, White Papers, etc.  Webcasts  Online Resources  Software   Tech Books   Conferences & Seminars  About SOCcentral.com
Copyright 2003-2013  Tech Pro Communications   1209 Colts Circle    Lawrenceville, NJ 08648    Phone: 609-477-6308
183.191  0.984375