July 20, 2012 -- Arasan Chip Systems, Inc. today announced the support of the new standard eMMC 4.51 in its SD4.0/ SDIO4.0/eMMC4.51 and SD3.0/ SDIO3.0/ eMMC4.51 Host Controller IP.

JEDEC published JESD84-B451: Embedded MultiMediaCard (eMMC), Electrical Standard (Version 4.51) in June 2012. Continuing the evolution of eMMC as an industry-leading memory standard for embedded non-volatile storage of system code, software applications and user data, the new v4.51 is a replacement of v4.5.

Arasan's SD4.0/ SDIO4.0/ eMMC4.51 and SD3.0/ SDIO3.0/ eMMC4.51 Host Controller IP handles all of the timing and interface protocol requirements to access these media as well as processing the commands in hardware, thereby scaling in both performance and access speeds. The IP supports connection to a single slot and performs multi-block writes and erases that lower access overhead. In addition, a host can utilize this IP to boot directly from an attached eMMC memory, thereby simplifying system initialization during power-up. The host interface is based on a standard 32-bit AXI bus which is used to transfer data and configure the IP.

JESD84-B451 eMMC v4.51 contains errata corrections and clarifications of the v4.5 standard, adds details of the power-supply requirements for e2MMC, defines pass-through commands for extended security protocols, and brings back the definitions of Secure Trim and Secure Erase functionality that were previously removed from the eMMC v4.5 standard for legacy backward compatibility, while maintaining the more favorable new alternate functions of Sanitize and Discard (introduced in v4.5) that allow improved performance and support of secure applications. Other than the changes described above, eMMC v4.51 maintains all functionality of the eMMC v4.5 standard, which focuses on improving the interaction between the host processor and the memory device at the interface, configuration and protocol level, resulting in potential gains in overall system reliability.

Availability

Arasan's SD3.0/ SDIO3.0/ eMMC4.51 and SD4.0/ SDIO4.0/ eMMC4.51 Host Controller IP are available immediately for licensing, including Verilog HDL of the IP core, verification IP, synthesis scripts, and documentation.

Posted by: John Miklosz