| Boost ASIC and SOC Performance by Matching Processor to Task through Automated Processor Generation | Company: Tensilica, Inc.
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The system architect faces a number of important decisions in creating the best SOC structure. Good choices early in the design process reduce silicon cost and power, increase system performance, and improve development and verification efficiency. This white paper explains the major decisions in architecting an SOC and guides the designer to a systematic approach to design structure using processors as the fundamental building blocks of the SOC. This design flow encourages wide use of processors as the default for implementing tasks and focuses on how to balance cost, performance, and flexibility within an SOC design framework.
The foundations for the design flow are these:
- Work top-down from the system’s essential I/O interfaces and computation requirements.
- Use processors pervasively to implement tasks
- When tasks have specific computational patterns, optimize the processor to fit the tasks
- When a task exceeds the capacity of an optimized processor, parallelize the task across processors
- When a group of tasks fits together within a processor’s capacity limit, map the tasks together onto one processor to minimize hardware cost, power, and communications overhead.
- Measure the communications traffic patterns and optimize the software and hardware interconnects around those patterns.
- Start with early, rough simulation of communication tasks and refine the system into detailed implementations of processors, software, and other blocks, all running in increasingly accurate simulations.
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Access the entire document on the Tensilica, Inc. website.
| E-mail Tensilica, Inc. for more information.
Read more about
Tensilica, Inc.
on SOCcentral.com |
| Keywords: Tensilica, configurable processors, intellectual property, IP,
| | 205/10233 11/19/2004 6371 801 | Add a comment or evaluation (anonymous postings will be deleted)
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