Power has become a first-order concern, right next to performance and area, for SOC designers, whether they are designing for portable mobile devices or for networking boxes. Optimizing for energy at an application and system level has the potential to cut processor and local memory energy requirements by up to half in most cases by making intelligent design trade-offs. Any power savings made at this early architectural level far outweigh any power savings made later at the RTL or physical design levels.

Currently, there are several low-power EDA design methodologies such as clock gating, voltage and frequency reduction, gate sizing and logic optimization, leakage reduction techniques, and low-power libraries and technology processes. These low-power methodologies can take months to implement and still not have the impact that system-level architectural decisions can have on energy efficiency when the architectural decisions are made before any RTL code has been written.

A lot of emphasis has been placed on guiding a SOC designer towards a performance and/or area optimized architecture, while making system choices such as memory sub-system design (banked memories versus a single large memory), interconnect (single bus versus a hierarchy of buses versus point-to-point interconnects), caches, etc. However, little has been done to guide designers towards an energy-efficient solution.