| Low-Power USB 2.0 PHY IP for High-Volume Consumer Applications | Company: Synopsys, Inc.
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The USB protocol has become a pervasive standard in the world of computing and consumer electronics. While few design teams would today contemplate designing their own USB intellectual property (IP), this semiconductor IP is far from commodity silicon. Synopsys introduces a second USB 2.0 PHY IP product line (titled DesignWare® USB 2.0 nanoPHY), which has been further optimized for low power, area, manufacturing cost and system performance targeted to mobile and high volume consumer applications. This offers designers a choice of highly-differentiated USB PHY cores for 0.13-micron processes and below.
By Gervais Fong, Product Marketing Manager, Synopsys, Inc.
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| Keywords: ASICs, ASIC design, FPGAs, field programmable gate arrays, FPGA design, DesignWare IP, intellectual property, cores, Universal Serial Bus, USB, low power design, low-power design, power analysis, power optimization, Synopsys,
| | 205/30498 1/20/2010 4076 185 | Add a comment or evaluation (anonymous postings will be deleted)
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