| IP Solutions for Synchronizing Signals that Cross Clock Domains | Company: Synopsys, Inc.
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This paper explains the many types of synchronization issues that occur when clocks and data signals cross from one clock domain to another. In all cases, the issues covered here involve clock domains that are asynchronous with respect to one another. Along with each issue, one or more DesignWare solutions is outlined. The topics and solutions include: Basic synchronization — DW_sync; Temporal event synchronization — DW_pulse_sync, DW_pulseack_sync; Simple data transfer synchronization — DW_data_sync, DW_data_sync_na, DW_data_sync_1c; Data flow synchronization — DW_fifo_s2_sf, DW_fifo_2c_df, DW_stream_sync; Reset sequencing — DW_reset_sync; Related clock system data synchronization — DW_data_qsync_hl, DW_data_qsync_lh.
By Rick Kelly, R&D Manager, Synopsys, Inc.
Access the entire document on the Synopsys, Inc. website.
| E-mail Synopsys, Inc. for more information.
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Synopsys, Inc.
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| Keywords: ASICs, ASIC design, EDA, EDA tools, electronic design automation, IP, intellectual property, cores, clocks, clocking, Synopsys,
| | 205/30504 1/20/2010 4470 151 | Add a comment or evaluation (anonymous postings will be deleted)
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