| High-Level "Plug-and-Play" Specification, Modeling and Synthesis of Pipelined Architectures with Bluespec’s PAClib | Company: Bluespec, Inc.
| | |
It is commonly assumed that the route to high-level specification and synthesis goes through C/ C++/ SystemC, particularly for "algorithmic" or "datapath-oriented" applications. This white paper presents a more effective and proven alternative. Starting with the basic computational functions of an application, one can build complex pipeline architectures in an easy "plug-and-play" manner by systematically composing powerful constructors from Bluespec’s PAClib (Pipelined Architecture Composers library).
The high level, yet transparent and precise, specification of the desired pipeline architecture quickly and predictably results in high quality implementations. Moreover, parametrization permits writing a single source code to encompass a wide variety of architectural choices, each of which may be more appropriate for different targets (e.g., mobile device vs. server). The technique relies on the advanced types, parametrization and atomic rule-based semantics of BSV (Bluespec SystemVerilog), unavailable in other design languages. BSV is also universal, seamlessly encompassing both datapath and control-oriented applications, whereas C/C++ high-level synthesis mostly applies to the former. Further, unlike C/C++, everything in BSV is synthesizable, so all refinements from initial models to final implementations can be executed on hardware platforms (e.g., FPGA/ emulation) at speeds orders of magnitude faster than the best software simulators, greatly benefiting validation, verification and early software development.
This white paper demonstrates these capabilities using the example of Inverse Fast Fourier Transform (IFFT), an important function in many wireless protocols that admits a rich space of architectures.
Access the entire document on the Bluespec, Inc. website.
| E-mail Bluespec, Inc. for more information.
Read more about Bluespec, Inc. on SOCcentral.com |
| Keywords: ASICs, ASIC design, FPGAs, field programmable gate arrays, FPGA design, EDA, EDA tools, electronic design automation, power analysis, power optimization, low power design, low-power design, electronic system level design, ESL, Bluespec,
| | 205/30512 1/21/2010 4134 266 | Add a comment or evaluation (anonymous postings will be deleted)
|
|
|
|
|
| | 0.25 |
|
|
| | |
|
|
Subscribe to SOCcentral's SOC Explorer Newsletter and receive news, article, whitepaper, and product updates bi-weekly.
|
|
|
Exec Viewpoint
The Many Faces of Low-Power Verification
 Ghislain Kaiser CEO, Docea Power
|
|
Exec Viewpoint
Maximizing the Value of Your Internal IP
 Warren Savage CEO, IPextreme
|
|
|
|
Barbara's Bytes
So, Just What Is ESL
 Barbara Tuck Senior Editor, SOCcentral
|
|
|
|
|
|
|
|
| Design Center |
| Whitepapers & App Notes |
|
|
|
|
|
| Live and Archived Webcasts |
|
|
|
|
|
| Newsletters |
|
|
|
|
|
|
About SOCcentral.com
Sponsorship/Advertising Information
|
|
|