We have all learned from experience there is no such thing as a free lunch — have you ever sat through a timeshare presentation? That's certainly the case with EDA tools, where the trade-off between price and risk can be both huge and precarious, particularly with the semiconductor industry’s push to 28-nm designs.

Early in my career I had an experience competing against a larger EDA company, trying to close a deal with a rapidly growing semiconductor company. A competitor offered their product for free for an entire year and told the customer, "Go ahead and use it for free for one year. Pay us at the end of the year only if you feel that you got the value out of the product that you needed."

We questioned the motivation of our competitor to provide adequate support on a product for which they were receiving no revenue. ... Then we received the call from the customer's purchasing manager telling us that we had been selected. The customer had determined that free was not worth the risk of failing to meet specs and missing the delivery deadline.

Modern chip design is a complex process full of challenges and surprises. Time to market, performance and cost management are critical determinants of the success or failure of a new chip design. As leading-edge semiconductor companies become proficient with 40-nm processes and move to 28nm, while eyeing 20nm on the horizon, new EDA innovations are required to meet the complex and unique needs for designing chips in these new processes.