SOCcentral: IP Reuse and Design Management in the SOC and IC Design Process (Gary Smith EDA 34292)

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Tuesday, May 21, 2013

IP Reuse and Design Management in the SOC and IC Design Process

Company: Gary Smith EDA

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The areas of SOC/IC design processes that engineers stated needed the most advancement in the next two years are EDA verification tools, IP collaboration tools, EDA design tools, and embedded software tools. Based on a recent survey of 465 SOC designers and managers, the top two areas for investment were verification tools at 63%, and IP (intellectual property) collaboration and reuse tools at 50%. 42% selected EDA design tools and 26% selected embedded software tools.

Access the entire document on the Gary Smith EDA website.

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Keywords: ASICs, ASIC design, FPGAs, field programmable gate arrays, FPGA design, EDA, EDA tools, electronic design automation, software development tools, IP, intellectual property, cores, Gary Smith EDA,

205/34292 7/17/2011 1519 99

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