As process technology pushes forward from 40nm to 28nm, unavoidable scaling effects are changing the electrical characteristics of the basic elements — the transistors and interconnect wires — with which chip designers must work. These new transistor-level challenges, in turn, are bringing about changes in the architecture, implementation, and performance of system-level ICs. And those chip-level changes are creating a new landscape in which system designers must find their way.
Today, in order to reduce the size of transistors, process developers must present chip designers with a complex battery of trade-offs involving speed, power, and cost. Chip designers must employ all their tools, including novel circuit designs, new architectural approaches, and fundamental changes in algorithms, to continue to offer greater performance and acceptable power at a competitive price. So far these techniques are effective, but they are not transparent to system designers. The 28-nm generation is firmly within a new era in system design: an era in which system designers must understand the challenges and decisions of the chip designers who supply the silicon.