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 Category: Tutorials, White Papers, App Notes, etc.: White Papers: Sunday, October 23, 2016
Using Boundary Scan to Link Design and Manufacturing Test  
Company: ASSET InterTech, Inc.
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In recent years, many in the electronics test industry have begun to realize that the value of boundary-scan test technology can be leveraged across the various phases in a product's life cycle. In particular, boundary scan can provide a link between design test and manufacturing test, producing long-term benefits in terms of greater efficiency and higher quality products. Such a link between design and manufacturing test will enable the benefits of standardizing and re-using design verification tests and PLD programming algorithms in manufacturing.

Of course, certain steps must be taken to allow for this linking. This paper will discuss the hardware and software infrastructure needed to achieve efficient test portability. In addition, design-for-test (DFT) guidelines and recommendations that improve the linkages among product design, prototype verification and high-volume manufacturing test will be highlighted. And, to demonstrate how some of these concepts can be applied, several case studies demonstrating effective boundary-scan test strategies will be described.

Access the entire document on the ASSET InterTech, Inc. website.

E-mail ASSET InterTech, Inc. for more information.

Read more about
ASSET InterTech, Inc.

Keywords: ASICs, ASIC design, FPGAs, field programmable gate arrays, FPGA design, PCB design, EDA, EDA tools, electronic design automation, boundary scan, BIST, built-in self-test, JTAG, design for manufacturing, design-for-manufacturing, DFM, ASSET InterTech,
205/39015 8/22/2012 1770 231
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