| A Processor and DSP IP Selection Checklist |
| Source: Tensilica, Inc. |
SOC designs are major, high-risk projects and most consist of many IP blocks-some developed in house and some purchased. Many of the most complex blocks are processors and DSPs. With their associated software-development tools, simulation models, and E ... read more |
| A Simulation Study of Simultaneous Switching Noise |
| Source: Sigrity, Inc. |
This paper describes a new methodology for simultaneous
switching noise (SSN) simulations by using a system level
signal integrity (SI) analysis software, which is combinations
of a quick full wave electromagnetic field solver for multiplelayer
str ... read more |
| A Socket-Based µController Design |
| Source: eASIC Corp. |
The FlexASIC structured-ASIC products are designed as general-purpose
configurable logic devices with standard-cell speed, density, and production
costs, and FPGA ease of use and prototype costs. Each member of the FlexASIC
product family contain ... read more |
| A Survey of Network-on-chip Proposals |
| Source: OCP International Partnership (OCP-IP) |
This paper gives an overview of state-of-the-art regarding the network-on-chip (NoC) proposals. NoC paradigm replaces dedicated, design-specific wires with scalable, general purpose, multi-hop network. Numerous examples from literature are selected
to ... read more |
| A Survival Guide for Selecting High-Quality IP |
| Source: Synopsys, Inc. |
As more functionality converges onto a single device, it naturally leads to an increasingly large number of IP blocks on a chip. Before you consider developing or buying IP, remember not all IP is created equally and securing high-quality IP is imperat ... read more |
| A System-On-Chip Bus Architecture for Thwarting Integrated Circuit Trojan Horses |
| Source: University of California, Electrical Engineering |
While the issue of Trojan ICs has been receiving increasing amounts of attention, the overwhelming majority of anti-Trojan measures aim to address the problem during verification. While such methods are an important part of an overall anti-Trojan strat ... read more |
| A Unified Approach of PM Noise Cancellation in Large RF Multitone Autonomous Circuits |
| Source: Mentor Graphics Corp. |
This paper presents a simulation method to
compute noise in autonomous and forced circuits
using the Harmonic Balance (HB) formulation.
Thanks to iterative linear solvers and multidimension
conversion matrices, it can handle
large multi-tone circu ... read more |
| Accelerating Functional Closure: Synopsys Verification Solutions |
| Source: Synopsys, Inc. |
This paper focuses on practical aspects of the verification process that can help reduce the time taken to reach functional closure. It is based on experiences of working directly with many leading edge semiconductor companies implementing modern verif ... read more |
| Accelerating Nanometer Yield Ramp with Yield Diagnostics |
| Source: Cadence Design Systems, Inc. |
The entire electronics industry's economic structure is based on getting ever more complex silicon at ever lower prices. The problems in silicon yield ramp are seriously threatening this model. Yield ramp is taking longer with each successive process g ... read more |
| Accelerating WiMAX System Design with FPGAs |
| Source: Altera Corp. |
WiMAX, or the IEEE 802.16 standard for broadband wireless access, is increasingly gaining in popularity as
a technology with significant market potential. This paper first provides an overview of the existing and
developing 802.16 standards and their ... read more |
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