Calypto was founded in 2002 by a team of experienced EDA and IC design technologists and is privately held, with funding from Tallwood Capital and Walden International Ventures.

SOCcentral Feature Articles
Low-Power RTL Report 2012	6/14/2012
Powering the Shift to HLS	12/6/2011
Re-timing Verification Using Sequential Equivalence Checking	3/24/2006
RTL Verification without Testbenches	7/11/2005
Articles Online
Reduce Power in Chip Designs with Sequential Clock Gating	12/17/2012
Powering Down: Enabling a Power Regression Flow for SoC Design	5/13/2010
How to Reduce Memory Power in SOC Designs	10/15/2009
How SLEC Improves Functional Verification	1/23/2009
Reducing Power Consumption in a Fiber Channel Switch	9/9/2008
Hardware Design Using ESL	2/11/2008
Utilizing Clock-Gating Efficiency to Reduce Power	1/15/2008
Leveraging C/C++ System Models for RTL Functional Verification	12/3/2007
RTL-ers Should Move to ESL	10/19/2007
Sequential Equivalence Checking for RTL Models	6/19/2006
Equivalency Checking Verifies Sequential Changes	6/20/2005

Tutorials, White Papers, etc.

Automating Sequential Clock Gating

Leveraging System Models for RTL Functional Verification Using Sequential Logic Equivalence Checking

Navigating the System to RTL Continuum

Sequential Equivalence Checking: A New Approach to Functional Verification of Datapath and Control Logic Changes

The Power of RTL Clock Gating

Utilizing Clock-Gating Efficiency to Reduce Power in RTL Designs

Verification without Testbenches

News
Calypto Catapult Integrates with Real Intent Ascent Lint for Reliable RTL Implementation Flow	2/11/2013
Core Logic Adopts Calypto PowerPro for Advanced RTL Power Reduction	10/8/2012
Calypto Leverages Core Technology to Expand Product Portfolio, Announces Catapult Low-Power High-Level Synthesis	5/29/2012
Calypto Delivers Bus Interface Libraries to Easily Connect High Level Synthesis Models to ARM Platform	2/28/2012
Calypto Partners with AcconSys to Provide Sales and Support in China	12/15/2011
Calypto Design Systems Acquires Mentor Catapult C Synthesis Tool	8/29/2011
Calypto Joins ARM Connected Community	7/22/2011
Concept Engineering's NLVIEW Visualization Engine Adopted by Calypto Design Systems	6/7/2011
Real Intent and Calypto Partner to Offer Integrated Tool Flow for RTL Power Optimization and Sign-Off	5/26/2011
Calypto Extends Power Optimization Capabilities with PowerPro 4.1	1/18/2011
Calypto Reduces Run-Time by 6X with Release of SLEC 5.1	1/11/2011
Advantest Selects Calypto's PowerPro CG and SLEC Pro to Reduce Power in ASIC Designs	9/1/2010
STARC, Calypto and Virage Logic Break New Ground With Industry's Lowest Power Design Flow	8/25/2010
Calypto Makes Major Enhancements to RTL Power Optimization Products	6/8/2010
Calypto's SLEC 5.0 Release Includes New Formal Verification Technology for Complex Loop Handling	6/7/2010
STARC Adopts Calypto’s PowerPro MG In Its STARCAD-CEL Version 4.0 Design Flow	4/14/2010
Virage Logic's 45-nm and 28-nm SiWare Memory Compilers Automatically Support Calypto's PowerPro MG tool	2/2/2010
Calypto Broadens Power Optimization Family with New PowerAdviser Flow	1/19/2010
Calypto Empowers Intrinsity to Deliver Power-Efficient 3rd-Party Processor Cores	11/23/2009
Calypto Delivers RTL Power Analyzer Based on Sequential-Analysis Technology	8/24/2009
Calypto Delivers Fully Automated Sequential Optimization Flow for High-performance IP Blocks	7/29/2009
Calypto Enables ESL Design and Verification of Complex Designs with 5X Capacity Improvement	7/20/2009
Calypto Delivers Automated Tool for Memory Power Optimization	6/23/2009
ARC, Calypto Team to Reduce Power in ARCs Video Subsystem Solution	1/23/2009
Calypto Announces New SLEC Release for Verification of Wireless, Video, Image Processing SOC Designs	11/11/2008
Calypto's PowerPro CG Cuts Power Consumption in Pixim's Latest Video Image Processor	10/28/2008
Calypto, Forte Collaboration Results in Advanced SystemC Design Flow	10/23/2008
Calypto Strengthens PowerPro CG with New Power Optimizations, VHDL Support	10/20/2008
Calypto's PowerPro CG Selected by AMD to Reduce Power in Processor Designs	8/5/2008
Calypto's Sequential Equivalence Checking Product Supports New Cadence C-to-Silicon Compiler	7/14/2008
Calypto Partners with HD Lab to Enable System Level Design Flows in Japan	6/6/2008
Calypto Delivers Optimized Power Flow with Cadence Design Systems	5/30/2008
Calypto to Offer Power Profiling Software Free of Charge at DAC	5/22/2008
Calypto Selects AST as Distributor and Technical Representative in Israel	5/14/2008
Calypto Releases PowerPro CG 2.0	3/24/2008
STARC Reduces SOC Design Power with Calypto's PowerPro CG Product	2/18/2008
Calypto Adds SLEC System-HLS to Product Line	1/14/2008
Mentor Graphics and Calypto Announce ESL Synthesis and Verification Flow Featuring Catapult C Synthesis and SLEC Sequential Equivalence Checker	1/14/2008
Carbon Joins MIPS Alliance Program	5/18/2007
Calypto Adds Common Power Format Support to PowerPro CG	4/10/2007
Calypto Debuts Sequential Power Optimization Solution for Automated RTL Power Reduction	3/26/2007
Calypto's SLEC RTL Product Selected by AMD to Verify Advanced Processors	3/14/2007
Calypto Extends Capabilities with Launch of SLEC CG for Verification of RTL Power Optimizations	11/6/2006
Calypto Expands India Operations	10/30/2006
Calypto Design Systems Expands European Presence	10/4/2006
Calypto Expands Sequential Analysis Capabilities with SLEC 2.0 Release	5/23/2006
Calypto and Forte Collaborate on Formal Verification and Behavioral Synthesis Tool Integration	10/4/2005
Calypto SLEC Sequential Equivalence Checker Deployed by Freescale Semiconductor PowerPC Team	6/10/2005
Calypto and Mentor Graphics Integrate Tools for Verifiable, Automated Path from System to RTL	6/2/2005
Verific Licenses HDL Component Software to Calypto Design Systems	5/10/2005
Calypto Introduces Sequential Logic Equivalence Checking Solution	4/25/2005
Calypto Design Systems Reveals Strategy to Bridge System and RTL Design	1/17/2005

Go directly to Calypto Design Systems, Inc. for more company and product information.