Page loading . . .

  
 Category: Vendors, Organizations & Universities: Vendors: Thursday, May 23, 2013
Noesis Technologies  
Email: info@noesis-tech.com
Website: www.noesis-tech.com/


Noesis Technologies specializes in the design, development and marketing of high quality, cost effective communication IP cores and provides VLSI design services. Its field of expertise include Forward Error Correction, cryptography and networking technology. In these fields, a broad range of high quality IP cores are offered.

News

Noesis Technologies Announces ComLab Platform

3/25/2013

Noesis Technologies Unveils ITU-T G.729A-Compliant Voice Codec Hardware Accelerator

11/27/2012

Noesis Technologies Achieves Xilinx Alliance Membership

6/18/2012

CEM Solutions Selects Noesis Technologies Audio Codec for Next-Generation VoIP Product

11/28/2011

Noesis Technologies Releases Fully Configurable N-point FFT/ IFFT Core

3/15/2010

Noesis Technologies Releases NIST FIPS-197 Compliant Low-Power AES IP Core

3/1/2010

Noesis Technologies Releases ITU G.704 E1 Framer/ Deframer IP Core

11/4/2009

Noesis Technologies Releases Fully Configurable Interleaver-Deinterleaver IP

6/12/2009

Noesis Technologies Releases AWGN Channel Emulator IP

1/20/2009

Noesis Technologies AnnouncesCompact Area Parameterizable Reed Solomon Decoder and Encoder IP Core

11/26/2007

Noesis Technologies Releases DVB-H Reed Solomon Decoder

11/5/2007


Go directly to Noesis Technologies for more company and product information.

Keywords: Noesis Technologies, IP,
206/24218 11/5/2007 996 193
Rate this vendor's website (anonymous postings will be deleted)




Designer's Mall
0.46875



 Search site for:
    Search Options

Subscribe to SOCcentral's
SOC Explorer
Newsletter
and receive news, article, whitepaper, and product updates bi-weekly.

Exec Viewpoint

The Many Faces
of Low-Power Verification


Ghislain Kaiser
CEO, Docea Power

Exec Viewpoint

Maximizing the Value of Your Internal IP


Warren Savage
CEO, IPextreme

Odd Parity

Lets' Go On
with the Show!


Mike Donlin
The Write Solution

Odd Parity Archive

Barbara's Bytes

So, Just What
Is ESL


Barbara Tuck
Senior Editor,
SOCcentral

SOCcentral Job Search

SOC Design
ASIC Design
ASIC Verification
FPGA Design
CPLD Design
PCB Design
DSP Design
RTOS Development
Digital Design

Analog Design
Mixed-Signal Design
DFT
DFM
IC Packaging
VHDL
Verilog
SystemC
SystemVerilog

Special Topics/Feature Articles
3D Integrated Circuits
Analog & Mixed-Signal Design
Design for Manufacturing
Design for Test
DSP in ASICs & FPGAs
ESL Design
Floorplanning & Layout
Formal Verification/OVM/UVM/VMM
Logic & Physical Synthesis
Low-Power Design
MEMS
On-Chip Interconnect
Selecting & Integrating IP
Signal Integrity
SystemC
SystemVerilog
Timing Analysis & Closure
Transaction Level Modeling (TLM)
Verilog
VHDL
 
Design Center
Whitepapers & App Notes
Live and Archived Webcasts
Newsletters


About SOCcentral.com

Sponsorship/Advertising Information

The Home Port  EDA/EDA Tools  FPGAs/PLDs/CPLDs  Intellectual Property  Electronic System Level Design  Special Topics/Feature Articles  Vendor & Organization Directory
News  Major RSS Feeds  Articles Online  Tutorials, White Papers, etc.  Webcasts  Online Resources  Software   Tech Books   Conferences & Seminars  About SOCcentral.com
Copyright 2003-2013  Tech Pro Communications   1209 Colts Circle    Lawrenceville, NJ 08648    Phone: 609-477-6308
190.206  0.546875