SOCcentral: Semiconductor Technology Academic Research Center (STARC) (2879)

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Wednesday, June 19, 2013

Semiconductor Technology Academic Research Center (STARC)

Address: 6F Yusen Shin Yokohama Bldg., 17-2, Shin Yokohama 3-chome, Kohoku-ku
Yokohama 222-0033 JAPAN
Phone: 81-45-478-3300
Email: info@starc.or.jp
Website: www.starc.jp/index-e.html

Funded by Japan's leading semiconductor manufacturers, the Semiconductor Technology Academic Research Center aims to strengthen the country's technological foundation concerning silicon semiconductors and enhance international competitiveness by commissioning universities for basic research and/or promoting joint projects with them on a sizable scale. By doing so, the center hopes to contribute to industrial growth not only on a domestic level, but also on a global scale. Further, the center will act as a place to nurture young engineers and researchers with a strong interest and passion in technological development.

News
STARC Certifies Pulsic's Unity Analog Router as Auto-Routing Tool in AMS IP-Reuse Reference Flow	3/26/2013
STARC Adopts Atrenta's Advanced RTL Power and Deep Submicron Test Solutions	5/19/2011
Mentor Graphics Calibre xACT 3D Field Solver Demonstrates High Accuracy and Performance in STARC Evaluation	3/28/2011
Pulsic's UniRoute Selected by STARC for STARCAD-AMS Analog/ Mixed-Signal Reference Flow	3/22/2011
Jedat's Amper Software Certified on STARC's Mixed-Signal Design Flow	3/16/2011
STARC Selects MunEDA WiCkeD for Variation-Aware Circuit Analysis and Optimization in the STARCAD-AMS Design Flow	1/31/2011
STARC Selects Solido Design Variation Tools for Next-Generation Analog/ Mixed-Signal Reference Flow	1/26/2011
STARC and Cadence Develop In-Design DFM for 32/28-nm Silicon Realization	1/24/2011
STARC Endorses FishTail for Automated Merging of Multi-Mode Design Constraints	10/27/2010
SpringSoft Validates Full Interoperability of Custom Chip Design Solutions with STARC 90nm iPDK	8/2/2010
STARC Adopts Calypto’s PowerPro MG In Its STARCAD-CEL Version 4.0 Design Flow	4/14/2010
Cadence Software Validated on STARC QA Database	2/1/2010
STARC Collaborates with Atrenta on EDA Tool Quality Management System	2/1/2010
STARC Adopts Incentia TimeCraft for Static Timing and Signal Integrity Analysis Solutions	12/17/2009
Atrenta SpyGlass-Constraints SDC Equivalence Verification Capability Adopted By STARC	12/2/2009
STARC and Cadence Collaborate to Develop Next-Generation Analog/ Mixed-Signal Reference Flow	10/19/2009
STARC Integrates Cadence Encounter Solution for Complex, Large-Scale Designs	7/9/2009
STARC Integrates Litho-Aware 45-nm Design Flow Using Cadence Encounter	7/9/2009
STARC and JEDA Join Forces to Ease Adoption of OSCI TLM2.0 Standard	1/27/2009
STARC Qualifies Cadence Encounter Conformal Constraint Designer for STARCAD-CEL Flow	1/19/2009
Aldec Delivers Clock Domain Crossing Solution	6/23/2008
Carbon Supports New STARC Transaction Level Modeling Guidelines	6/3/2008
STARC Adds Atrenta Tools to Reference Flow	4/24/2008
STARC Adopts Cadence Encounter Timing System for Static Timing Analysis Signoff	4/7/2008
STARC Establishes Variation-and-Yield-Aware Design Methodology Using Mentor Graphics Calibre LFD	3/27/2008
STARC Endorses FishTail for Timing Exception Verification and Generation	3/19/2008
CoWare and STARC Integrate SystemC TLM Methodology	1/21/2008
STARC Adopts Synopsys PrimeTime VX as the Variation-Aware Timing Tool for Its STARCAD-CEL Methodology	1/14/2008
Cadence Works with STARC to Address 65-nm DFM Challenges	7/10/2007
Aldec Releases STARC Based Linting Tool	6/11/2007
Brion Collaborates with STARC on its Tachyon-Based Workflow	5/23/2007
STARC to Develop Low-Power Pride Reference Flow Using Common Power Format	5/21/2007
STARC to Use Mentor Graphics TestKompress ATPG Tool to Target Delay Defects	5/9/2007
Magma FineSim Spice Supports STARC HiSIM Model with Proven 20x Faster Circuit Simulation and Nearly Exact Correlation to Silicon	3/26/2007
STARC adopts Altos’ Characterization Products for STARCAD-CEL Design Methodology	3/26/2007
STARC Standardizes on Calibre YieldAnalyzer as Reference Tool in DFM Flow for Critical Area Extraction	1/26/2007
STARC and Simucad to Add HiSIM Model to Enhance Prototype Shuttle Service	1/23/2007
Clear Shape Partners with STARC to Develop Comprehensive DFM Flow	1/17/2007
STARC Deploys Synopsys Design Compiler Topographical Technology in New 65nm Methodology	12/11/2006
STARC Adds Magma’s Quartz SSTA Statistical Analysis and Optimization Solution to Variation-Aware 65- and 45-nm Design Methodology	7/24/2006
STARC Joins SPIRIT Consortium as First Japanese Institute to Support Design Meta-Data Standardization	7/19/2006
STARC Selects Chipidea PLL for Advanced Semiconductor Design Effort	6/6/2006
STARC Adopts IC Compiler to Boost Efficiency of Production Flow	3/27/2006
Mentor Graphics and STARC Partner to Develop Improved at-Speed Test Methods for Nanometer Design	1/25/2006
STARC Standardizes on FishTail for Timing Exception Generation	1/25/2006
STARC Completes VSIA QIP Metric Beta Program	12/13/2005
STARC Standardizes on Synopsys Tools for 90-nm Low Power Design in STARCAD-21 Flow	6/14/2005

Go directly to the Semiconductor Technology Academic Research Center (STARC) site for additional information.

Keywords: Semiconductor Technology Academic Research Center (STARC)

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