Page loading . . .
Source Navigator for Verilog is full featured tool for editing and navigating through large projects with many Verilog ... read more
Splint is a tool for statically checking C programs for security vulnerabilities and coding mistakes. With minimal eff ... read more
Verilator is the fastest free Verilog HDL simulator, and beats many commercial simulators. It compiles synthesizable V ... read more
Verilog2C++ is a Verilog to C++ translation program that translates a C++ class of a Verilog design using a cycle-accu ... read more
Subscribe to SOCcentral'sSOC ExplorerNewsletterand receive news, article, whitepaper, and product updates bi-weekly.
Exec Viewpoint
The Many Facesof Low-Power Verification
Ghislain KaiserCEO, Docea Power
Maximizing the Value of Your Internal IP
Warren SavageCEO, IPextreme
Lets' Go Onwith the Show!
Mike DonlinThe Write Solution Odd Parity Archive
Barbara's Bytes
So, Just What Is ESL
Barbara TuckSenior Editor,SOCcentral
SOC Design ASIC Design ASIC Verification FPGA Design CPLD Design PCB Design DSP Design RTOS Development Digital Design
Analog Design Mixed-Signal Design DFT DFM IC Packaging VHDL Verilog SystemC SystemVerilog
About SOCcentral.com
Sponsorship/Advertising Information