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 Category: Magazine & Journal Articles Online: Current Month: Wednesday, May 22, 2013
Designing a NVMe-Compliant PCIe SSD  
Publication: Chip Estimate Corp.
Contributor: IP-Maker
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September 4, 2012 -- NVM Express is definitely the key technology solution to enable the broad adoption of SSD using the PCIe interface. The remaining question is: how to design a PCIe SSD compliant to the specification?

Drivers for PCIe SSDs are not standardized like for USB with the mass storage class. That means that each SSD provider needs to develop its own software driver. That participates to the high cost of a PCIe SSD. In addition, most of current PCIe SSDs are based on the integration of a PCIe-to-SATA bridge and SATA-based NandFlash controllers. This solution is efficient for a PCIe Gen 1 interface. That becomes not viable with Gen 2 and Gen 3. To sustain a so important throughput, too many SATA channels in parallel would be required. The last point is about the data transfer control. With this current solution, the management is done by the host processor, wasting time when waiting for the end of NAND Flash read or write.

By Jerome Gaysse. (Gaysse is with IP-Maker.)

This brief introduction has been excerpted from the original copyrighted article.


View the entire article on the Chip Estimate Corp. website.

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Keywords: ASICs, ASIC design, FPGAs, field programmable gate arrays, FPGA design, nonvolatile memory, non-volatile memory, NVM, PCI Express, PCIe, IP, intellectual property, cores, Chip Estimate, IP-Maker,
602/39131 9/4/2012 755 86


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