| How to Make Your SOC Simulation Run 100X Faster with Accelerated Verification IP Featured | Sponsor: Cadence Design Systems, Inc.
Webcaster: EE Times Education & Training
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May 30, 2012 -- Verification teams commonly find that the large size of their SOCs exceeds the ability of logic simulators to effectively verify them. Simulation acceleration addresses this problem by coupling logic simulation with a hardware accelerator to deliver performance 100 to 1000 times faster than logic simulation. Until recently, the use of simulation acceleration has been limited by the inability to stimulate the design's interfaces at a rate fast enough to keep up with the accelerator.
Cadence now addresses this problem by providing a line of Accelerated VIP (AVIP) supporting several standard interfaces to unlock the inherent speed of simulation acceleration. The AVIP supports multiple user interfaces targeting various stages of product verification. In particular, AVIP enables reuse of simulation test benches based on the popular Universal Verification Methodology (UVM).
This webinar covers:
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An overview of the current verification methods used to verify, IP, SOCs, and systems.
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Detailed exploration of simulation acceleration including strengths and limitations.
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The function of accelerated VIP (AVIP) in supporting simulation acceleration.
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The various user interfaces of AVIP, the trade-offs of each, and the benefits for SOC verification and HW/SW integration.
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Examples of success achieved on real designs.
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Go directly to the EE Times Education & Training webcast site to view this presentation. Registration may be required.
| | Keywords: ASICs, ASIC design, FPGAs, field programmable gate arrays, FPGA design, EDA, EDA tools, electronic design automation, verification IP, intellectual property, cores, Cadence Design Systems, EE Times Education & Training
| | 336/38537 5/30/2012 544 26 | |
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| | 0.015625 |
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