Sponsor: Aldec, Inc.
Webcaster: Aldec, Inc.
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May 3, 2012 -- Experienced users of VHDL simulation with testbenches appreciate the additional layer of safety that coverage analysis gives them. But are all kinds of coverage equally beneficial? While code coverage is certainly useful, it really verifies quality of the testbench, not the design itself. In this webinar, we demonstrate how to improve the quality of the design using — with help of OS-VVM.
Agenda
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Introduction
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Code Coverage flavors and their usage
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Property Coverage - close relative of Assertions
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Smart Functional Coverage in VHDL using OS-VVM
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Conclusion
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Go directly to the Aldec, Inc. webcast site to view this presentation. Registration may be required.
| | Keywords: ASICs, ASIC design, FPGAs, field programmable gate arrays, FPGA design, EDA, EDA tools, electronic design automation, property coverage, functional coverage, functional verification, testbenches, VHDL, OS-VVM, Aldec,
| | 336/38760 5/3/2012 139 17 | |
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