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Transaction-Level Modeling and Advanced Verification Come Together with SystemC and SystemVerilog
Despite the ongoing debate whether SystemC or SystemVerilog is the better language for system design and verification, there may be no need to choose between them. They can be effectively used in a complementary manner to facilitate the successful adoption of an advanced verification methodology that employs constrained random test generation, functional coverage, assertions, and transaction-level modeling (TLM).
Both languages share the ability to model higher levels of abstraction by supporting object oriented programming. Both languages contain verification components such as randomization. There are some differences, for instance SystemC supports TLM, including the describing, recording, and viewing of transactions at high levels of abstraction. SystemVerilog does not yet fully support TLM, but it delivers significant verification advantages through the support of assertions, functional coverage, and improved constrained random test generation. The two languages overlap somewhat in their capabilities, which provides a smooth transition when building systems using both languages.
Read the entire article from Mentor Graphics Corp. on SOCcentral.
SystemC Training Course
This introductory course is intended for designers who are investigating language alternatives for high-level design. SystemC is an open source C++ library that is emerging as a standard for high-level design and system modeling. Designers who complete the course will gain a clear understanding of the fundamentals of SystemC and considerations affecting its choice as a language for high-level design.
The introductory online course can normally be completed in 4-6 hours. As with any design, verification, or programming language, comprehensive training is necessary to take full advantage of the language and improve your productivity. Willamette HDL, a leader in SystemC training, produced material for this course and offers advanced training on www.whdl.com.
View the course on the Forte Design Systems, Inc. website.
SystemC Tutorial
This SystemC Tutorial is taken from material in the introductory chapters of the Doulos SystemC Golden Reference Guide. The company will be adding to it approximately once a month. The first part, now available, covers a brief introduction to SystemC, and then an example of a simple design. The parts to come in the future will go into more detail about Debugging, Hierarchical Channels, and Primitive Channels and the Kernel.
View the course on the Doulos, Ltd. website.
Utilizing SystemC for Design and Verification
The number one reason for the use of SystemC is the significantly increased simulation performance at the TLM level over executable platforms modeled at the RT level using Verilog or VHDL. SystemC TL models are fast enough to serve as a software development platform allowing for early software development and for co-simulation of hardware and software. Both TL and functional models are fast enough for system level architectural modeling and analysis.
The second reason for SystemC use is functional verification. The same executable platform that is used to develop the software is often used for verification of the entire system. This verification occurs early on in a project and the TLM becomes a golden reference for the entire system. Because SystemC is C++, it has a number of inherent properties, such as classes, templates and
inheritance, that lend themselves to verification. These capabilities are extended with the SystemC Verification Library (discussed later) making SystemC a powerful verification language as well as modeling language.
This exhaustive examination includes dozens of graphics, a glossary and code appendix.
 Read the entire paper on the Mentor Graphics Corp. website.
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