Category: Special Topics: SystemC:

Monday, February 08, 2010

SystemC

Transaction-Level Modeling and Advanced Verification Come Together with SystemC and SystemVerilog

Despite the ongoing debate whether SystemC or SystemVerilog is the better language for system design and verification, there may be no need to choose between them. They can be effectively used in a complementary manner to facilitate the successful adoption of an advanced verification methodology that employs constrained random test generation, functional coverage, assertions, and transaction-level modeling (TLM).

Both languages share the ability to model higher levels of abstraction by supporting object oriented programming. Both languages contain verification components such as randomization. There are some differences, for instance SystemC supports TLM, including the describing, recording, and viewing of transactions at high levels of abstraction. SystemVerilog does not yet fully support TLM, but it delivers significant verification advantages through the support of assertions, functional coverage, and improved constrained random test generation. The two languages overlap somewhat in their capabilities, which provides a smooth transition when building systems using both languages.

Read the entire article from Mentor Graphics Corp. on SOCcentral.

SystemC Training Course

This introductory course is intended for designers who are investigating language alternatives for high-level design. SystemC is an open source C++ library that is emerging as a standard for high-level design and system modeling. Designers who complete the course will gain a clear understanding of the fundamentals of SystemC and considerations affecting its choice as a language for high-level design.

The introductory online course can normally be completed in 4-6 hours. As with any design, verification, or programming language, comprehensive training is necessary to take full advantage of the language and improve your productivity. Willamette HDL, a leader in SystemC training, produced material for this course and offers advanced training on www.whdl.com.

View the course on the Forte Design Systems, Inc. website.

SystemC Tutorial

This SystemC Tutorial is taken from material in the introductory chapters of the Doulos SystemC Golden Reference Guide. The company will be adding to it approximately once a month. The first part, now available, covers a brief introduction to SystemC, and then an example of a simple design. The parts to come in the future will go into more detail about Debugging, Hierarchical Channels, and Primitive Channels and the Kernel.

View the course on the Doulos, Ltd. website.

Utilizing SystemC for Design and Verification

The number one reason for the use of SystemC is the significantly increased simulation performance at the TLM level over executable platforms modeled at the RT level using Verilog or VHDL. SystemC TL models are fast enough to serve as a software development platform allowing for early software development and for co-simulation of hardware and software. Both TL and functional models are fast enough for system level architectural modeling and analysis.

The second reason for SystemC use is functional verification. The same executable platform that is used to develop the software is often used for verification of the entire system. This verification occurs early on in a project and the TLM becomes a golden reference for the entire system. Because SystemC is C++, it has a number of inherent properties, such as classes, templates and inheritance, that lend themselves to verification. These capabilities are extended with the SystemC Verification Library (discussed later) making SystemC a powerful verification language as well as modeling language.

This exhaustive examination includes dozens of graphics, a glossary and code appendix.

Read the entire paper on the Mentor Graphics Corp. website.

Designer's Mall

SOCcentral news items about SystemC

MegaChips Selects Forte Design Systems' High-Level Synthesis Software (1/27/2010)

Mentor Graphics Catapult C Adds SystemC Synthesis and Expands Full-Chip Capabilities (1/25/2010)

Synopsys Introduces SystemC TLM-2.0 SuperSpeed USB 3.0 Models (1/12/2010)

Top EDA Companies Endorse Tensilica's Pin-Level SystemC Models (12/7/2009)

AMCC Chooses Carbon Model Studio for System-Level Modeling and Validation (11/18/2009)

Technical Presentations from North American SystemC Users Group Meeting Now Online (11/13/2009)

OSCI Introduces SystemC Synthesis Subset Draft Standard; Opens for Public Review (11/9/2009)

CoWare and ARM Partner to Enable Rapid Configuration of AMBA NIC-301 Network Interconnect-Based SOC Designs in SystemC (10/22/2009)

VaST Enhances CoMET and METeor with OSCI TLM2 Support and Open SystemC Modeling Library (8/25/2009)

Forte Announces SystemC Synthesis Success with Fujitsu Microelectronics Europe (8/5/2009)

Open SystemC Initiative Unveils Technical Working Group Milestones at DAC (7/31/2009)

Virtutech Announces Simics Full-System Checkpointing for SystemC Based Transaction-Level Modeling (7/29/2009)

Cofluent Design Closes Modeling Gap for Virtual Platforms (7/20/2009)

NXP Deploys Integrated CoWare and ARM Cortex Processor-Based Solution in its Virtual Prototyping Environment (7/20/2009)

Siemens Uses Cofluent Design to Create Models for Virtual Platform Simulation (7/20/2009)

Aldec Delivers $1,995 Mixed-Language Simulator to FPGA Market (7/13/2009)

ChipVision Enhances PowerOpt with Major Advancements in Power Optimization and C++/ SystemC Language Support (7/7/2009)

Forte Releases Latest Version of Cynthesizer SystemC High-Level Synthesis (6/30/2009)

Casio Selects Cadence C-to-Silicon Compiler for High-Level Synthesis (6/8/2009)

Cadence Speeds Systems Development with Automated Transaction-Level Verification (5/21/2009)

Free Open SystemC Initiative Video Tutorial Details TLM-2.0 in Action (5/6/2009)

CircuitSutra Releases STARC Transaction Level Modeling Guide Compliant Demo SystemC Model Set (4/23/2009)

OCP-IP Delivers New Advanced SystemC TLM Kit (4/22/2009)

Open SystemC Initiative Spearheads Definition of Standards for Interoperable Instrumentation of Models (2/25/2009)

Cadence Extends the Open Verification Methodology to Include SystemC and e Language Support (2/23/2009)

CircuitSutra Partners with GreenSocs to Provide High-Quality SystemC based SOC Modelling Services (2/16/2009)

OVP Simulator Breaks SystemC TLM-2.0 Performance Barrier (2/16/2009)

CoWare and Rambus Announce Unique ESL Architecture Design Environment for Rambus' XDR Memory Architectue (2/10/2009)

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Magazine & Journal articles on SystemC

An UML-Driven Interface Generation Approach for SoC Design Design & Reuse (11/2/2009)

Timing Annotation of Untimed Functional Models for Architecture Use-Case Design & Reuse (8/27/2009)

Bridging from ESL Models to Implementation Via High-level Hardware Synthesis EDA Tech Forum (7/15/2009)

Troubleshooting a Transaction-Level Model EDN Magazine (6/11/2009)

A SystemC/TLM Based Methodology for IP Development and FPGA Prototyping EDA DesignLine (11/3/2008)

Modeling Embedded Systems Using SystemC Extensions EDA Tech Forum (9/1/2008)

Why SystemC Virtual Platforms Are the Answer SCDsource (6/24/2008)

Regression Test for OCP SystemC Channel Models EDA DesignLine (9/4/2007)

Using SystemC Reference Models in SystemVerilog Testbenches SOCcentral (4/2/2007)

C-based Design Methodology Accelerates ASIC/FPGA Design Cycles EDA DesignLine (1/7/2007)

SystemVerilog and SystemC: Two Standards Used Together to Design SOCs SOCcentral (7/14/2006)

Transaction-Level Modeling and Advanced Verification Come Together with SystemC and SystemVerilog SOCcentral (3/24/2006)

Are You Designing with Too Many Significant Figures? FPGA and Programmable Logic Journal (3/21/2006)

Preview USB Performance in an SOC Design Using a SystemC Virtual Platform EDN Magazine (2/16/2006)

Learn To Manage All Kinds of Complexity with SystemC Electronic Design Magazine (9/29/2005)

A Tale of Two Languages: SystemC and SystemVerilog Chip Design Magazine (6/1/2005)

System Verification for Reconfigurable Processor-Based Systems using SystemC SOCcentral (6/1/2005)

Getting to a Higher Level Electronic Design Magazine (3/31/2005)

Synthesis from C in Electronic System Level (ESL) Design SOCcentral (2/16/2005)

Back to the Language Roots Embedded Systems Design (embedded.com) (12/20/2004)

How to Choose a Verification Methodology eeDesign (EE Times EDA News) (7/9/2004)

Celoxica Adds New C Tools eeDesign (EE Times EDA News) (7/1/2004)

Easing Today’s Verification Language Bedlam Chip Design Magazine (5/1/2004)

The Search for the Perfect Language EDN Magazine (2/5/2004)

SystemC Verification Library Speeds Transaction-Based Verification eeDesign (EE Times EDA News) (2/24/2003)

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Tutorials, White Papers and Conference Papers on SystemC

A Framework for Embedded System Specification under Different Models of Computation in SystemC Design Automation Conference (DAC)

A Model Driven Design Environment for Embedded Systems Design Automation Conference (DAC)

A Timing-Accurate Modeling and Simulation Environment for Networked Embedded Systems Design Automation Conference (DAC)

An Area Estimation Methodology for FPGA Based Designs at SystemC-Level Design Automation Conference (DAC)

Assertion Based Verification, ESL to Gate JEDA Technologies, Inc.

Developing Transaction-level Models in SystemC CoWare, Inc.

Formal Techniques for SystemC Verification (11.1) Design Automation Conference (DAC)

Functional Verification of SiCortex Multiprocessor System-on-a-Chip (48.4) Design Automation Conference (DAC)

GreenBus: A Generic Interconnect Fabric for Transaction Level Modeling Design Automation Conference (DAC)

Language Extensions to SystemC: Process Control Constructs (3.3) Design Automation Conference (DAC)

Leveraging System Models for RTL Functional Verification Using Sequential Logic Equivalence Checking Calypto Design Systems, Inc.

Maintaining Consistency Between SystemC and RTL System Designs Design Automation Conference (DAC)

Model-Driven Validation of SystemC Designs (3.2) Design Automation Conference (DAC)

Modeling OCP Interfaces in SystemC: Standards built on top of OSCI’s TLM-2 OCP International Partnership (OCP-IP)

Native SystemC Assertion (NSCa) JEDA Technologies, Inc.

NSCa and PSL: Why Native Assertion Is Iportant in SystemC? JEDA Technologies, Inc.

PANEL: Building a Standard ESL Design and Verification Methodology: Is It Just a Dream? Design Automation Conference (DAC)

Performance Analysis of Different Arbitration Algorithms of the AMBA AHB BUS Design Automation Conference (DAC)

SUNMAP: A Tool for Automatic Topology Selection and Generation for NoCs Design Automation Conference (DAC)

SystemC based SoC Communication Modeling for the OCP Protocol OCP International Partnership (OCP-IP)

SystemC Training Course Forte Design Systems, Inc.

SystemC Transaction Level Models and RTL Verification Design Automation Conference (DAC)

SystemC Tutorial Doulos

SystemC Tutorial ASIC World

SystemC: An Introduction for Beginners electrosofts.com

TLM: Crossing Over from Buzz to Adoption (25.1) Design Automation Conference (DAC)

TLM-2.0 in Action: An Example-based Approach to Transaction-Level Modeling and Model Interoperability Open SystemC Initiative (OSCI)

Unified TLM 2.0 Coverage Measurement JEDA Technologies, Inc.

Using Program Specialization to Speed SystemC Fixed-Point Simulation Formal Sciences, Inc.

Utilizing SystemC for Design and Verification Mentor Graphics Corp.

Verification Methodologies in a TLM-to-RTL Design Flow (11.3) Design Automation Conference (DAC)

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