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Category: Special Topics: VHDL:

Friday, September 10, 2010

VHDL

Featured Articles

Aldec Evita VHDL Tutorial

Aldec has developed its VHDL Tutorial to educate traditional schematic and mixed mode based users with the basic fundamentals for designing with the VHDL hardware description language. This VHDL centric tutorial will help ease the learning curve and include a series of questions and answers to test your knowledge at the end of each chapter.

The tutorial includes an interactive overview of the VHDL hardware description language as well as including a complete VHDL Reference Guide with over 150 topics providing definitions and examples of key VHDL terms and concepts.

Registration is required to download this tutorial. But well worth it.

View the tutorial on the Aldec website.

Designer's Mall

SOCcentral news items about VHDL

WaveFormer Lite Generates Mixed-Signal HDL Test Benches for All FPGA Design Flows (8/11/2010)

Northwest Logic Verifies Compatibility of Its IP Cores with Aldec RTL Simulators (8/2/2010)

HDL Design House Announces HVT MX25L VITAL Behavioral Model (7/22/2010)

Dolphin Integration and Infolytica Enable Mechatronic System Simulation Using MagNet and MotorSolve coupled with SMASH (7/16/2010)

Latest Release of Aldec's Riviera-PRO Supports OVM/UVM (6/8/2010)

Mentor Graphics 0-In Formal Version 3.0 Brings New Level of Automation to Formal Verification (6/1/2010)

Altium Adds Aldec FPGA Simulation Technology to Altium Designer (5/25/2010)

Real Intent Improves Its Fast, Low-Noise Electronic Design Linter (5/13/2010)

Aldec Releases RTL Simulator with Enhanced Assertions and Xilinx SecureIP Support (12/24/2009)

Aldec Adds DO-254/ ED-80 Library to HDL Design Rule Checker (12/10/2009)

Maia EDA Launches New Automated Verification Tool (12/10/2009)

Oasys Design Systems Adds VHDL Support to RealTime Designer (11/18/2009)

Aldec Announces Low-Cost Linux RTL and Gate-level Simulator (11/17/2009)

EMA Partners with Aldec to Provide Cadence OrCAD Users a Complete FPGA Design Solution (10/16/2009)

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Magazine & Journal articles on VHDL

Reusable VHDL IP In the Real World Design & Reuse (2/18/2010)

A Set of VHDL IPs to Evaluate Performance of Netwoks-on-Chip Design & Reuse (10/22/2009)

VHDL Moves Toward 4.0 EDA Tech Forum (6/1/2008)

Open Verification Methodology Allows Reusable Testbenches SCDsource (4/29/2008)

Accellera VHDL Standard EDA DesignLine (10/25/2007)

Getting to a Higher Level Electronic Design Magazine (3/31/2005)

Back to the Language Roots Embedded Systems Design (embedded.com) (12/20/2004)

Mixed HDLs plus HVL: Part 2, Using Specman Elite in a Mixed Verilog/VHDL Chip Verification Environment Chip Design Magazine (11/1/2004)

Mixed HDLs plus HVL: Part 1, Using Specman Elite in a Mixed Verilog/VHDL Chip Verification Environment Chip Design Magazine (9/1/2004)

The Search for the Perfect Language EDN Magazine (2/5/2004)

VHDL-200x Improves Design and Verification Productivity eeDesign (EE Times EDA News) (11/7/2003)

Using VHDL-AMS to Model Complex Heterogeneous Systems, Part 1 EDN Magazine (8/21/2003)

Using VHDL-AMS to Model Complex Heterogeneous Systems: Part 2 EDN Magazine (8/21/2003)

Toil and Trouble in ASIC Synthesis EDAVision (4/1/2002)

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Tutorials, White Papers and Conference Papers on VHDL

16b/20b Encoder/Decoder Xilinx, Inc.

170 MHz FIFOs Using the Virtex Block SelectRAM+ Feature Xilinx, Inc.

8051 Microcontroller Interface Xilinx, Inc.

A Comparison of Two VHDL Memory Modeling Techniques Free Model Foundry

Advanced High-Level HDL Design Techniques for Programmable Logic Synplicity, Inc.

An Area Estimation Methodology for FPGA Based Designs at SystemC-Level Design Automation Conference (DAC)

An High-End Realtime Stream Processing Library for FPGAs (49.2) Design Automation Conference (DAC)

An Introductory VHDL Tutorial Green Mountain Computing Systems, Inc.

ASIC Design Flow Tutorial Hacettepe University

Automated Nonlinear Macromodeling of Output Buffers for High-Speed Digital Applications Design Automation Conference (DAC)

Automatic Translation of Software Binaries onto FPGAs Design Automation Conference (DAC)

Coding Techniques for Bus Functional Models In Verilog, VHDL, and C++ SynaptiCAD, Inc.

Design Tips for Arithmetic Functions Xilinx, Inc.

Designer's Guide to VHDL Doulos

Digital Integrated Circuit Design The University of Bolton

Efficient Timing Closure Without Timing Driven Placement and Routing Design Automation Conference (DAC)

Evita Interactive VHDL Tutorial Aldec, Inc.

FIFOs Using Virtex-II Block RAM Xilinx, Inc.

FPGAs: Under the Hood National Instruments Corp.

Free Models: What Are They? How Are They Used? How Can They Be Free? Free Model Foundry

Hardware/Software Co-Verification with RTOS Application Code Mentor Graphics Corp.

High Speed FIFOs In Spartan-II FPGAs Xilinx, Inc.

I2C Bus Controller Xilinx, Inc.

IEEE Std VHDL 1076.1-1999: The Analog and Mixed-Signal Extensions for VHDL Mentor Graphics Corp.

Introduction to VHDL electrosofts.com

It's About Time: Requirements for the Verification of Nanometer-scale ICs Cadence Design Systems, Inc.

Manchester Encoder-Decoder for CoolRunner CPLDs Xilinx, Inc.

Modeling Safe Operating Area in Hardware Description Languages (21.2) Design Automation Conference (DAC)

NanoMap: An Integrated Design Optimization Flow for a Hybrid Nanotube/ CMOS Dynamically Reconfigurable Architecture (17.1) Design Automation Conference (DAC)

Optimal Pipelining of the I/O Ports of Virtex-II Multipliers Xilinx, Inc.

Performance Analysis of Different Arbitration Algorithms of the AMBA AHB BUS Design Automation Conference (DAC)

RTL Coding Styles That Yield Simulation and Synthesis Mismatches Sunburst Design, Inc.

SMBus Controller Xilinx, Inc.

System for Coarse Grained Memory Protection In Tiny Embedded Processors (13.2) Design Automation Conference (DAC)

System Level Design and Verification Using a Synchronous Language Formal Sciences, Inc.

SystemC: An Introduction for Beginners electrosofts.com

SystemVerilog Implicit Port Connections: Simulation and Synthesis Sunburst Design, Inc.

SystemVerilog Tutorial ASIC World

Towards Automatic Exploration of Arithmetic Circuit Architectures Design Automation Conference (DAC)

Transposed Form FIR Filters Xilinx, Inc.

UARTs Xilinx, Inc.

Utilizing SystemC for Design and Verification Mentor Graphics Corp.

Verilog Tutorial Yankee Bush Software

VHDL Language Guide Accolade Design Automation

VHDL Tutorial Yankee Bush Software

VHDL Tutorial University of Erlangen-Nürnberg

VHDL Tutorial ASIC World

VHDL Verification Course Stefan Doll

Virtex-II SelectLink Communications Channel Xilinx, Inc.

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