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SOCcentral is carrying out a comprehensive, open-ended survey of low-power design methodologies and the factors that affect your design decisions and the reasons that your company is implementing — or not implementing — various low-power techniques.
To provide your input, or view the results for those SOCcentral visitors who have already participated, go to the Low-Power Design Survey now.
Your participation is critical to the value of this survey, so please give the design community a few minutes of your time. Thanks.
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Featured Articles
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Power Is on Everybody's Mind
The increased prevalence of power gating presents a number of challenges that make emulation a good platform for functional verification. First, power gating generally occurs at the system level, often controlled by the software or by the primary processor in the design. Realistically testing power gating requires the execution of embedded software on the full-chip netlist. At this level, high gate-counts and long software tests — often including the operating system (OS) boot — can easily extend beyond the reach of simulation. SOC emulators offer the capacity and the execution speeds required to test power-gating scenarios in a reasonable time-frame. ... read more.
By Lauro Rizzatti, GM of EVE-USA
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Use the Power of Your SOC to Verify Its Low-Power Design Features
The worlds of system-on-chip (SOC) development and low-power design are almost completely intertwined these days. Most SOCs are developed for portable consumer devices where battery life can make or break a product. If the SOC is part of an implantable medical device, power consumption can make or break a patient. Even wall-powered systems may have to meet regulatory or market requirements for power consumption. It's a rare SOC project that doesn't need to use low-power-design techniques to some extent or another. ... read more.
By Thomas L. Anderson, Vice President of Marketing, Breker Verification Systems, Inc.
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 Low-Power RTL Report 2012
This article is based on a report that covers trends in the area of low-power design, based on an independent, global RTL power analysis and optimization survey. By analyzing this comprehensive feedback from design engineers and engineering management, we can better understand the effort spent on reducing power consumption in the design cycle, as well as the popular low power techniques being applied. This becomes especially critical with scaling technology nodes to 65nm and beyond.
Read the entire article from Calypto Design Systems, Inc. on SOCcentral.
Building Energy-Efficient ICs from the Ground Up
 Power consumption has moved to the forefront of digital-IC development as component sizes shrink and insulating layers on gates become thinner. To enable the adoption of advanced low-power techniques by mainstream users, there is a need for a design flow that holistically addresses the architecture, design, verification, and implementation of low-power designs. The Common Power Format (CPF) has emerged as an effective means to capture the design's power intent early on and to communicate this intent throughout the design flow.
Read the entire article from Cadence Design Systems, Inc. on SOCcentral.
Understanding the Low Power Abstraction
The increasing importance of power considerations in electronic-system design has highlighted the need for a model of active-power control and its effects. This model may be referred to as the "Low Power Abstraction," since it is used primarily to reduce power consumption through active-power management. It introduces new concepts such as "corruption" and its implications. Similarly, but orthogonally, the increasing importance of system-level design has led to a transaction-level model that excludes some of the signal-level details of the digital model in order to focus on the system-level behavior that emerges from the integration of subcomponents.
Read the entire article from Mentor Graphics Corp. on SOCcentral.
Challenges and Requirements for Power-Aware Debugging
Power format standards, such as the Common Power Format (CPF) and the Unified Power Format (UPF), are evolving to establish a power definition that can be used throughout the design, verification, and implementation stages. While development of a consistent power definition seems promising, it has direct implications on the complex verification issues that engineers face in debugging power-aware designs and the types of solutions needed to address them.
Read the entire article from SpringSoft, Inc. on SOCcentral.
The Evolution of Power Format Standards
 The Silicon Integration Initiative's (Si2's) contribution of the Open Low-Power Methodology (OpenLPM) to the IEEE in 2011 marked an important milestone in the development of power-format standards for the industry. Cadence, among many other industry leaders, supports this contribution because it shows the most-promising path for the industry to converge on one power-format standard. Methodology convergence, however, is a pre-requisite for future power-format convergence. The current status of all power formats is shown here.
Read the entire article from Cadence Design Systems, Inc. on SOCcentral.
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Magazine & Journal articles on Power Analysis, Optimization & Low-Power Design |
| Reducing Energy Consumption in ICT Applications Using the Dynamic Bus Voltage Architecture EDN Magazine (4/17/2013) |
| Developing Power-Sensitive, Low-Current MCU Designs EE Times Power Management Designline (4/4/2013) |
| Smart Decap-Insertion Methodology Design & Reuse (3/18/2013) |
| Guidelines for Early Power Analysis EE Times EDA Designline (2/11/2013) |
| Reducing Power in AMD Processor Cores with RTL Clock-Gating Analysis EE Times EDA Designline (2/4/2013) |
| An ESD-Efficient, Generic Low-Power Wake-Up Methodology in an SOC Design & Reuse (1/23/2013) |
| Formal Methods for Power-Aware Verification EE Times EDA Designline (12/17/2012) |
| Power and Thermal Modeling and Analysis of Multi-Die Packages SOCcentral (12/17/2012) |
| Reduce Power in Chip Designs with Sequential Clock Gating Electronic Design Magazine (12/17/2012) |
| Building Energy-Efficient ICs from the Ground Up SOCcentral (12/5/2012) |
| Designing Low-Energy Embedded Systems from Silicon to Software EDN Magazine (11/28/2012) |
| Embedded MCUs Get Smarter As Energy Efficiency Takes Centre Stage EE Times MCU Designline (11/27/2012) |
| Speeding Power Estimation from Weeks to Hours EE Times EDA Designline (11/19/2012) |
| Emulation Delivers System-Level Power Verification Tech Design Forum (10/26/2012) |
| How Low Power Becomes No Power Electronic Products Magazine (10/26/2012) |
| Generate an Interface Rule for Low-Power Consumer Devices Electronic Design Magazine (10/24/2012) |
| Memory Solution Addressing Power and Security Problems in Embedded Designs EE Times EDA Designline (10/22/2012) |
| Use the Power of Your SOC to Verify Its Low-Power Design Features SOCcentral (9/1/2012) |
| Challenges and Requirements for Power-Aware Debugging SOCcentral (8/27/2012) |
| Power Noise Reduction by Optimizing the Dynamic Power Signature of Digital ICs EE Times EDA Designline (7/30/2012) |
| Power Awareness in RTL Design Analysis EE Times EDA Designline (7/23/2012) |
| The Evolution of Power Format Standards SOCcentral (7/16/2012) |
| How to Reduce Energy Consumption in MCU-based Systems that Need to Monitor Outside Inputs EE Times MCU Designline (7/9/2012) |
| Understanding the Low Power Abstraction SOCcentral (7/6/2012) |
| Optimizing FPGAs for Power: A Full-Frontal Attack EE Times Militray & Aerospace Highlights (6/18/2012) |
| Low-Power RTL Report 2012 SOCcentral (6/14/2012) |
| Thread Synchronization Techniques for Better Multicore System Power/ Performance Trade-Offs EE Times Embedded (6/12/2012) |
| Power-Aware Emulation Tests Power Islands EE Times EDA Designline (6/4/2012) |
| Power: A Significant Challenge in EDA Design EDN Magazine (5/24/2012) |
| Hierarchical Methods for Power-Intent Specification EE Times EDA Designline (4/30/2012) |
| A Modeling Approach for Power-Integrity Simulation in 3D-IC Designs EE Times EDA Designline (4/27/2012) |
| Design-for-Power Methodology EE Times EDA Designline (4/20/2012) |
| Design Considerations for Power-Sensitive Embedded Devices EE Times Embedded (4/17/2012) |
| Building Predictability into Your Low-Power Design Flow EE Times EDA Designline (4/16/2012) |
| Early and Accurate Power Analysis: Myth or Reality? EE Times EDA Designline (4/11/2012) |
| Considerations for Writing UPF for a Hierarchical Flow EE Times EDA Designline (4/6/2012) |
| Define Drain-Current Conditions when Calculating Power for Multicore SOCs EE Times Automotive Designline (1/5/2012) |
| The Many Facets of Power Management for Computer Peripherals EE Times Power Management Designline (12/16/2011) |
| Powering the Shift to HLS SOCcentral (12/6/2011) |
| Handling Clock Synchronization During Power-Driven Synthesis SOCcentral (10/27/2011) |
| The Basics of Low-Power Programming on the Cortex-M0 EE Times Embedded (10/25/2011) |
| Minimize Leakage Power in Embedded SOC Designs with Multi-Vt Cells EE Times Embedded (8/6/2011) |
| Power-Integrity Simulation Keeps Your Planes Perfect EDN Magazine (7/14/2011) |
| Designers Take a Fresh Look at Power Management System Design New Electronics Magazine (7/12/2011) |
| Power Optimization for Low-Power SOCs Targeting Mobile Devices New Electronics Magazine (6/29/2011) |
| Managing Power in Embedded Applications Using Dual Operating Systems EE Times Embedded (6/28/2011) |
| Reduce SOC Device/ Package Leakage/ Power with Improved Power-Management Protocols EE Times Embedded (6/27/2011) |
| Comparing Hot Swap IC Solutions in Server Power Reporting-Part 2 EE Times Power Management Designline (6/16/2011) |
| Comparing Hot Swap IC Solutions in Server Power Reporting-Part 1 EE Times Power Management Designline (6/10/2011) |
| A Case for Custom Power Management ASICs Design & Reuse (6/8/2011) |
| Power Optimization in Image Superscalar IP Design & Reuse (5/26/2011) |
| Advanced Power Management in Embedded Memory Subsystems Design & Reuse (5/19/2011) |
| DSPs with PCI Express Interface Extend Connectivity While Improving Performance and Power Efficiency EE Times Signal Processing DesignLine (4/25/2011) |
| Cache Evaluation Software: A Dynamically Configurable Cache Simulator Design & Reuse (4/21/2011) |
| Implementing Different Power Features in an IP Design & Reuse (4/7/2011) |
| The Missing Pieces in Power Modeling; Who's Going to Provide Them Chip Design Magazine (4/1/2011) |
| System Awareness Improves SOC Power Management EE Times Power Management Designline (3/18/2011) |
| Using Copper Pillars to Increase Analog IC Power Dissipation EE Times Power Management Designline (2/14/2011) |
| Advances in Energy-Storage Technology Power Wireless Devices EDN Magazine (2/3/2011) |
| An RTL-to-GDSII Approach for Low Power Design: A Design for Power Methodology EE Times EDA Designline (1/12/2011) |
| Debugging for Power Consumption New Electronics Magazine (1/10/2011) |
| Quest Continues for the "Sweet Spot" in Configurable ASIC/ SOC Design RTC Magazine (1/1/2011) |
| Power Aware Verification of ARM-Based Designs EE Times Embedded (11/4/2010) |
| Discovering the Last Unrealized Power Reduction EDN Magazine (9/13/2010) |
| Embedded Systems Power Down EDN Magazine (7/29/2010) |
| Chip Power Model for Co-Design SOCcentral (7/12/2010) |
| Low Power: The Next Big Challenge for FPGA Designers SOCcentral (7/12/2010) |
| Exploring Multicore Power Management with Modeling and Simulation EE Times Embedded (6/29/2010) |
| Power Analysis of Clock Gating at RTL EE Times EDA Designline (6/17/2010) |
| Power Optimization In Image Superscalar IP Design & Reuse (6/17/2010) |
| Power-Grid Analysis on SOC Graphics Chip Design EDN Magazine (6/17/2010) |
| Reducing Switching Power with Intelligent Clock Gating EE Times Programmable Logic Designline (6/17/2010) |
| Continuum (Analog) Analysis of Power Integrity SOCcentral (5/28/2010) |
| Power Management for Optimal Power Design EDN Magazine (5/27/2010) |
| What Is Power Debugging? EE Times Embedded (5/27/2010) |
| Powering Down: Enabling a Power Regression Flow for SoC Design EE Times Embedded (5/13/2010) |
| Low-Power Design Applications for Formal Verification SOCcentral (5/7/2010) |
| Greening Multiprocessor Design EE Times EDA Designline (3/22/2010) |
| Power Delivery Network Design Requires Chip-package-system Co-Design Approach EE Times EDA Designline (3/15/2010) |
| Green In: Multi-Engine GPS, DIMM Buffers, and Health-Certified USB Stack Embedded Computing Design (2/16/2010) |
| Green Up: Leading Edge of "Green" Mixed-Signal Embedded Computing Design (2/16/2010) |
| Achieving Extremely Low Power for Portable Apps Electronic Products Magazine (2/1/2010) |
| Field-Programmable Power Is Essential for ASSPs Electronic Products Magazine (2/1/2010) |
| Low-Power Design Is Here to Stay EE Times EDA Designline (1/16/2010) |
| Low-power LDPC Decoder Created Using High-Level Synthesis EE Times EDA Designline (1/13/2010) |
| Using An FPGA to Tame the Power Beast In Consumer Handheld MPUs EE Times Programmable Logic Designline (1/13/2010) |
| Automating Advanced Clock-Gating Techniques During High-Level Synthesis SOCcentral (12/10/2009) |
| Clock Gating: Smart Use Ensures Smart Returns EDN Magazine (12/4/2009) |
| Take Simple Steps Toward Extreme Low-Power Design Electronic Design Magazine (11/20/2009) |
| Enable Low-Power Design with FPGAs EE Times Programmable Logic Designline (10/30/2009) |
| FPGA Architectural Power-Saving Techniques at 40nm EDN Magazine (9/23/2009) |
| Why Programmability Is Now a Game Changer Electronic Engineering Times (EE Times) (9/10/2009) |
| The Virtual Vehicle: Making Power Management Easier EE Times EDA Designline (8/11/2009) |
| Making ASIC Power Estimates Before the Design EDN Magazine (7/23/2009) |
| Balancing the Power Budget Components in Electronics (CIE) (6/30/2009) |
| Should Dual-Rail Go Mainstream in Deep Nanometer Era? Electronic Design Magazine (6/29/2009) |
| Design Techniques for FPGA Power Optimization DSP-FPGA (6/15/2009) |
| Power vs. Performance: The Ultimate DSP Design Challenge DSP-FPGA (6/15/2009) |
| Power Management: Parametric Design By Software EE Times Power Management Designline (6/7/2009) |
| HDL Design Methods for Low-Power Implementation Design & Reuse (5/28/2009) |
| The Drive to Lower Power DSP-FPGA (5/15/2009) |
| Estimating Power in FPGA Designs EDN Magazine (4/23/2009) |
| Integrated Power Management, Leakage Control and Process Compensation Technology for Advanced Processes Design & Reuse (3/16/2009) |
| How to Reduce Power Consumption in CPLD Designs with Power Supply Cycling EE Times Programmable Logic Designline (3/11/2009) |
| Behavioral Design Drives Low-Power Silicon EE Times EDA Designline (2/16/2009) |
| Power-Aware FPGA Design: Part 1 EE Times Programmable Logic Designline (2/4/2009) |
| Designing for State Retention SOCcentral (12/12/2008) |
| A Turn-off: Power Management Complicates Life for Verification Engineers EDN Magazine (10/16/2008) |
| Reducing Power in High-Performance Designs Chip Estimate Corp. (10/7/2008) |
| The Need to Address Power During Manufacturing Test EE Times EDA Designline (10/6/2008) |
| Reducing Power Consumption in a Fiber Channel Switch EE Times EDA Designline (9/9/2008) |
| Power Trends Point to a Knowledge of Integration EE Times EDA Designline (7/22/2008) |
| Automating Advanced Low-Power Multi-Voltage Design SOCcentral (6/9/2008) |
| Industry Leaders Define Next Priorities for Low Power SOCcentral (6/9/2008) |
| Low Power Is Now a High Priority SOCcentral (6/9/2008) |
| Multi-Corner, Multi-Mode Power Closure: The New Dimension in IC Design SOCcentral (6/9/2008) |
| Power Has Consequences, So Chill Out! SOCcentral (6/9/2008) |
| A Power Integrity Wall Follows the Power Wall! SOCcentral (3/25/2008) |
| High Efficiency Challenges Power-Management Design Electronic Design Magazine (3/13/2008) |
| Low-Power Design for Analog/Mixed-Signal IP EE Times EDA Designline (3/4/2008) |
| Power-Intent Standards Vie for Designers' Loyalties Electronic Design Magazine (2/14/2008) |
| Power Integrity and Energy-Aware Floorplanning SOCcentral (1/16/2008) |
| Utilizing Clock-Gating Efficiency to Reduce Power EE Times EDA Designline (1/15/2008) |
| Rethinking How to Decrease Power Consumption EDN Magazine (1/10/2008) |
| Creating a Unified Power Flow SOCcentral (11/12/2007) |
| Make Front-End Power Predictable EDN Magazine (10/19/2007) |
| Low Power Design Specification from RTL through GDSII EE Times EDA Designline (7/9/2007) |
| Practical Power Network Synthesis for Power-Gating Designs EE Times EDA Designline (6/5/2007) |
| Taking a Bite Out of Power: Techniques for Low-Power ASIC Design EDN Magazine (5/24/2007) |
| Extreme Low-Power Design EDN Magazine (5/10/2007) |
| A Methodology for Front-End Ppower Predictability EDN Magazine (4/18/2007) |
| Total Power Optimization in RTL-to-GDSII Implementation Flow EE Times EDA Designline (3/12/2007) |
| Integrating Power Awareness into IC Design EE Times EDA Designline (3/1/2007) |
| New EDA Tools Improve Low Power Design EE Times EDA Designline (2/19/2007) |
| Improve Performance and Reduce Power Consumption in Mixed-Signal Designs EE Times RF & Microwave Designline (2/14/2007) |
| How to Architect, Design, Implement, and Verify Low-Power Digital ICs EE Times EDA Designline (1/29/2007) |
| Top 10 Methods for ASIC Power Minimization: Part 1 EE Times Power Management Designline (1/8/2007) |
| Optimize Your DSPs for Power and Performance EE Times Signal Processing DesignLine (1/4/2007) |
| How to Reduce Power Using I/O Gating (CPLDs) versus Sleep Modes (FPGAs) EE Times Programmable Logic Designline (9/20/2006) |
| Power Integrity Analysis for Billion Transistor Full-Custom Designs EE Times EDA Designline (9/17/2006) |
| Using Statistical Activity for Power Estimation eeDesign (EE Times EDA News) (7/24/2006) |
| Pulse-Latch Approach Reduces Dynamic Power eeDesign (EE Times EDA News) (7/17/2006) |
| Is Chip Design Different After 90nm? EDN Magazine (7/6/2006) |
| Using Dynamic and Static Power Rail Analysis to Maximize Results with Minimum Effort SOCcentral (6/26/2006) |
| FPGAs Balance Lower Power, Smaller Nodes Drip by Drip EDN Magazine (6/8/2006) |
| Dual Threshold Voltages and Power-Gating Design Flows Offer Good Results EDN Magazine (2/2/2006) |
| Rail-Signoff Analysis Ensures SoC Power Integrity Electronic Design Magazine (1/19/2006) |
| Power Considerations in Designing with 90m FPGAs EE Times Programmable Logic Designline (11/23/2005) |
| Tackling Test Challenges for Low-Power Design eeDesign (EE Times EDA News) (11/7/2005) |
| Reliable Sign-off at Smaller Nodes EDN Magazine (5/12/2005) |
| Low-Power Flow Enables Multi-Supply Voltage ICs Electronic Engineering Times (EE Times) (3/21/2005) |
| A Methodology for IC Power Grid Design eeDesign (EE Times EDA News) (3/11/2005) |
| Placement-Driven Power Optimization at 90nm and Below SOCcentral (3/7/2005) |
| Accurate Power-Analysis Techniques Support Smart SOC-Design Choices EDN Magazine (12/7/2004) |
| The Why, Where and What of Low-Power SoC Design eeDesign (EE Times EDA News) (12/2/2004) |
| Power Islands: The Evolving Topology of SoC Power Management Design & Reuse (11/1/2004) |
| Symmetric Design Technique Facilitates Power Analysis eeDesign (EE Times EDA News) (9/3/2004) |
| Hot chips? ... Not! Efficient Power Management in the 90-nm Foundry Reference Flow Chip Design Magazine (9/1/2004) |
| Modeling and Design Techniques Reduce 90nm Power eeDesign (EE Times EDA News) (8/6/2004) |
| Heat Wave: FPGAs Confront Increasing, Evolving Power Consumption EDN Magazine (8/5/2004) |
| Power Management IP: Coming to the Rescue for Nanometer Design Electronic Products Magazine (8/1/2004) |
| Squeeze Play: Wring the Power Out of Your Design EDN Magazine (2/19/2004) |
| Reshaping the SoC Power Design Flow eeDesign (EE Times EDA News) (2/6/2004) |
| Design-Planning Guidelines Prevent Chip Surprises EDN Magazine (2/5/2004) |
| Design and Evaluation of Power-Efficient SoCs Electronic Engineering Times (EE Times) (1/22/2004) |
| Low-Power SRAMs Improve System Picture Electronic Engineering Times (EE Times) (1/22/2004) |
| Speedy Processor Runs on Low Power Electronic Engineering Times (EE Times) (1/22/2004) |
| System-Level Tools Slash SoC Dynamic Power Electronic Engineering Times (EE Times) (1/22/2004) |
| Designing with Hard Power Constraints Electronic Engineering Times (EE Times) (1/15/2004) |
| Islands in the Power Management Storm Electronic Engineering Times (EE Times) (1/15/2004) |
| Non-Linear Effects in Low-Power Sub-100nm Designs Electronic Engineering Times (EE Times) (1/15/2004) |
| Techniques for Energy-Efficient SoC Design eeDesign (EE Times EDA News) (7/24/2003) |
| Low-power Design Techniques Span RTL-to-GDSII Flow eeDesign (EE Times EDA News) (6/9/2003) |
| A System-Level Methodology for Low-Power Design eeDesign (EE Times EDA News) (5/2/2003) |
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